Bjorn Eriksson wrote:
>
> Re:
> > I'm surprised to learn that AMD has ported the bug to the SC5x0
> > series, as it has actually been known for years now (albeit only
> > to some insiders; I found out the hard way only about 4 weeks ago).
>
> Well... You needn't find this problem yourself since it's listed in the
> errata and it's been mentioned both on the Usenet and on this list (I
> forwarded a patch a year ago or so).
I did try to look for an errata for the AMD SC410 (which is the one I use),
but I didn't find any on the AMD web-site (probably for the reason you
state at the bottom), and I only joined this list two months ago...
> The SC520 errata says (Fix planned for the B0 stepping) :
>
> <<When a Transmit Holding Register Empty interrupt is generated by a UART
> (THRE bit set in UARTxLSR and ETHREI bit set in UARTxINTENB) it will
> deassert when the UARTxINTID register is read.
That, in itself, is not an error.
> To be 16450/550 compatible the interrupt should be reissued if the ETHREI
> bit is subsequently cleared and then set. However, this is not happening on
> either UART. The interrupt is not reissued nor does the UARTxINTID register
> read a value of 2 (THRE interrupt).
On the SC410, the INTID does indeed read 2 (THRE int), but the LSR bit THRE
is *not* set (and that's the one the Linux serial.c tests, not the INTID!)
> When the next byte is written to the UARTxTHR register a new interrupt is
> generated when the Transmitter Holding Register becomes empty again.>>
Yeah, the interrupt is generated all right, but the LSR does not reflect this
(the THRE bit in the LSR seems to be set one bit clock *after* the interrupt
is asserted).
> Oh, BTW, this info - the errata - is stamped as confidential information. BS
> IMNSHO.
Agree.
--
cheers
Anders Larsen
e-mail: alarsen AT baumerident DOT com
Q: What does the CE in Windows CE stand for?
A: Caveat Emptor
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