Hi *,
So, here's my little hack to enable the NSC PC-87108
It's still too much hard coded, but I'll try to make it a little more
generic so I can configure other Chips as well. later :-)
I still don't know what DMA's are required with the nsc-ircc kernel
module. Does it use the DMA_Swap Bit to excange TX and RX DMA's? Maybe i
should try to understand the source then, or someone enlightens me.
Cu,
Flo
,--. *************************************************************
| } Florian Schiel, mailto:[EMAIL PROTECTED] **
|--\ /--\ ./~\. Student der Elektrotechnik, FH M�nchen **
| ) {---' { } Administrator LNT-EIkon, TU-M�nchen **
L___/ \__. `\_/' ***************************************
"Technology is a constant battle between manufacturers producing bigger and
more idiot-proof systems and nature producing bigger and better idiots."
/*
File: set-nsc.c
*****************************************************************************
Configure the NSC PC-87108 IrCC and set IO-Ports, IRQ, DMA
First quick and dirty hack. everything is static
Author: Florian Schiel <[EMAIL PROTECTED]> Aug 2000
Some lines are taken from 'findchip.c' from Dag Brattli's irda-utils
Compile with:
gcc -O2 -o set-nsc set-nsc.c
Chip-Documentation can be found here:
http://www.nsc.com/dasd/pc87108.pdf
CHANGES:
21.10.2000/beo added Register description
TODO:
Clean up, command-line, etc.
******************************************************************************
Config Register description:
BAIC
Bits | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
Funct | res | res | res | irqbc | irqinv| enbnk | bas1 | bas0 |
Reset | x | x | x | 0 | 0 | 0 | 0 | 0 |
bas0, bas1: Serial Base Address
0,0 = 3E8h
0,1 = 2E8h
1,0 = 3F8h
1,1 = 2F8h
enbnk: Enable Register Bank
0 = disabled
1 = enabled
irqinv: IRQ Polarity Invert
0 = active high
1 = active low
irqbc: IRQ Outpout Buffer
0 = open drain
1 = totem pole
res: Reserverd
set to 0
CSRT
Bits | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
Funct | slerr |txdsl1 |txdsl0 |rxdsl1 |rxdsl0 |irqsl2 |irqsl1 |irqsl0 |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
irq_sl2,1,0 IRQ Signal Select
0,0,0 = None
0,0,1 = IRQ 3
0,1,0 = IRQ 4
0,1,1 = IRQ 5
1,0,0 = IRQ 7
1,0,1 = IRQ 9
1,1,0 = IRQ 11
1,1,1 = IRQ 15
rxd_sl1,0 RX DMA Select
0,0 = None
0,1 = DMA 0
1,0 = DMA 1
1,1 = DMA 3
txd_sl1,0 TX DMA Select
0,0 = None
0,1 = DMA 0
1,0 = DMA 1
1,1 = DMA 3
slerr DMA Signal Selection Error (r/only Bit)
set to 1 if (txd_sl == rxd_sl)
#MCTL - Mode Control
Bits | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
Funct | res | mtest | res |auxirsl|busysl | busy2 | nom | deven |
Reset | x | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
dev_en: Device Enable
0 = disabled
1 = enabled
nom: Normal Operating Mode
0 = low power
1 = normal operation
busy Busy Status (r/only Bit)
1 if (data transfer in progress)
busy_sl Busy Output Select
0 = Busy on GPIO3 (if enabled as output)
1 = Busy on 'Busy Status'
auxir_sl AUXSL Output Select (?)
0 = AUX_IRRX on GPIO2
1 = AUX_IRRX on AUX__IRRX Bit
mtest Manufacturing Test
Write 0's
res Reserved
Write 0's
GPDIR - GPIO Direction
Bits | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
Funct | res | res | res | res | dir3 | dir2 | dir1 | dir0 |
Reset | x | x | x | x | 0 | 0 | 0 | 0 |
dir3,2,1,0 GPIO Direction Select
0 = input
1 = output
res Reserverd
write 0's
GPDAT - GPIO Data
Bits | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
Funct | res | res | res | res | dat3 | dat2 | dat1 | dat0 |
Reset | x | x | x | x | x | x | x | x |
dat3,2,1,0 GPIO Data Bits
0 = low
1 = high
res Reserverd
write 0's
DID - Device Identification Register
read-only: returns 1xh
********************************************************************************
*/
#include <stdio.h>
#include <asm/io.h>
/* Base IO Address for configuration registers of the '108*/
#define cfg_base 0x0ea
/* Config registers for the '108 */
#define CFG_BAIC 0x00
#define CFG_CSRT 0x01
#define CFG_MCTL 0x02
#define CFG_GPDIR 0x03
#define CFG_GPDAT 0x04
#define CFG_DID 0x05
/* Dirty binary output */
void print_bin(int base, int value)
{
printf("Index: %3i Value: %3i =>",base,value);
if (value & 0x80) printf(" 1");
else printf(" 0");
if (value & 0x40) printf(" 1");
else printf(" 0");
if (value & 0x20) printf(" 1");
else printf(" 0");
if (value & 0x10) printf(" 1");
else printf(" 0");
if (value & 0x08) printf(" 1");
else printf(" 0");
if (value & 0x04) printf(" 1");
else printf(" 0");
if (value & 0x02) printf(" 1");
else printf(" 0");
if (value & 0x01) printf(" 1\n");
else printf(" 0\n");
}
main()
{
int reg;
int index;
int val;
if (!ioperm(0x0, 0x3ff, 1)) {
printf("Reading Ports\n");
/* Read address and interrupt control register (BAIC) */
index=CFG_BAIC;
outb(index, cfg_base);
print_bin(index,inb(cfg_base+1));
/* Base: 2E8h and Enabled
0x05 = 0 0 0 0 0 1 0 1 */
outb(0x05, cfg_base+1);
print_bin(index,inb(cfg_base+1));
index=CFG_CSRT;
outb(index, cfg_base);
print_bin(index,inb(cfg_base+1));
/* IRQ 3, RXDMA 1, TXDMA 3
0x71 = 0 1 1 1 0 0 0 1 */
outb(0x71, cfg_base+1);
print_bin(index,inb(cfg_base+1));
index=CFG_MCTL;
outb(index, cfg_base);
print_bin(index,inb(cfg_base+1));
/* Enabled, Normal, Busy to GPIO3
/* 0x0b = 0 0 0 0 1 0 1 1 */
outb(0x0b, cfg_base+1);
print_bin(index,inb(cfg_base+1));
index=CFG_GPDIR;
outb(index, cfg_base);
print_bin(index,inb(cfg_base+1));
/* GPIO3 to Output for 'Busy'
0x08 = 0 0 0 0 1 0 0 0 */
outb(0x08, cfg_base+1);
print_bin(index,inb(cfg_base+1));
index=CFG_GPDAT;
outb(index, cfg_base);
print_bin(index,inb(cfg_base+1));
index=CFG_DID;
outb(index, cfg_base);
print_bin(index,inb(cfg_base+1));
}
else printf("Sorry, no I/O Permission\n");
return 0;
}
