Thanks a lot.
Your program is completely useless for *337 chips but I was so inspired
that managed to create my own: for my chip. See attachement.
Now I see in findchip -v:
Found NSC PC87338 Controller at 0x398, DevID=0x0b, Rev. 2
SIR Base 0x2f8, FIR Base 0x2f8
IRQ = 3, DMA = 2
Enabled: yes, Suspended: no
UART compatible: yes
Half duplex delay = 0 us
But now, when I try to load nsc-ircc module, I get (in dmesg):
nsc-ircc, Wrong chip version ff
Any ideas about this problem?
BTW, I think it would be good to include some controller enabling code
into the nsc module of the kernel. Any objections? Probably, the author
of the module could do this work (probably, using my humble code:)?
Regards,
Sergey
/*********************************************************************
*
* Filename: set-nsc338.c
* Version: 0.1
* Description: Hardware enabler for NSC PCx7338 infrared controllers
* Status: Experimental.
* Author: Sergey V. Udaltsov <[EMAIL PROTECTED]>
* Created at: Wed Oct 25 20:00:00 2000
*
* Copyright (c) 1999-2000 Sergey V. Udaltsov, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
********************************************************************/
#include <sys/types.h>
#include <stdio.h>
#include <unistd.h>
#include <fcntl.h>
#include <asm/io.h>
#define BASE_CFG_IO 0x398 // ask findchip for exact value
#define IRQ 3
#define DMA 2
#define BASE_IO 0x2F8
/* Config registers for the '338 */
#define CFG_FER 0x00
#define CFG_FAR 0x01
#define CFG_PTR 0x02
#define CFG_PNP0 0x1b
#define CFG_PNP1 0x1c
#define CFG_S2BAL 0x46
#define CFG_S2BAH 0x47
#define CFG_PNP3 0x4f
void nsc_init( int enable )
{
int cfg_base;
int reg;
cfg_base = BASE_CFG_IO;
reg = inb(cfg_base);
if ( reg == 0xff)
{
fprintf( stderr, "Error: no chip at 0x%03x\n", cfg_base);
exit(2);
}
outb(CFG_PNP1, cfg_base);
reg = inb(cfg_base+1);
outb( reg | (IRQ << 4), cfg_base+1);
outb(CFG_PNP3, cfg_base);
reg = inb(cfg_base+1);
outb( reg | ( ((DMA + 1) << 3) | (DMA+1) ), cfg_base+1); //same for T & R
outb(CFG_S2BAL, cfg_base);
reg = inb(cfg_base+1);
outb( ( BASE_IO >> 2 ) & 0xFE, cfg_base+1);
outb(CFG_S2BAH, cfg_base);
reg = inb(cfg_base+1);
outb( ( BASE_IO >> 8 ) & 0xFC, cfg_base+1);
if (!enable) return;
outb(CFG_FER, cfg_base);
reg = inb(cfg_base+1);
outb( reg | 0x04 , cfg_base+1); // Enable!
}
int main( int argc, char * argv[] )
{
int enable = 0,i;
char * arg;
if ( argc > 1 )
{
arg = argv[1];
for ( i = argc; --i>0; arg++)
{
if ( !strcmp( arg, "-e" ) ) enable = 1;
else
{
fprintf( stderr, "Invalid argument: %s\n", arg );
exit(3);
}
}
}
if (ioperm(0x0, 0x3ff, 1))
{
fprintf( stderr, "Set i/o permission\n");
exit(1);
}
nsc_init( enable );
return 0;
}
