Ted and LT,
I think this are the two things you wanted that were located in:
/src/tar-files/testing/direct_add/ht6560b.c
/src/tar-files/testing/direct_add/qd65xx.c
/src/tar-files/testing/direct_add/qd65xx.h
First Petr and Samuel, are these good to go into 2.4.0 ??
Cheers,
Andre Hedrick
The Linux ATA/IDE guy
/*
* TEMPORARY VERSION FOR HT6560A MODEL TESTING!!!!!
*
* MODIFIED FOR BOTH A AND B VERSIONS
* 2000-07-16 Petr Soucek <[EMAIL PROTECTED]>
*/
/*
* linux/drivers/block/ht6560b.c Version 0.07 Feb 1, 2000
*
* Copyright (C) 1995-2000 Linus Torvalds & author (see below)
*/
/*
*
* Version 0.01 Initial version hacked out of ide.c
*
* Version 0.02 Added support for PIO modes, auto-tune
*
* Version 0.03 Some cleanups
*
* Version 0.05 PIO mode cycle timings auto-tune using bus-speed
*
* Version 0.06 Prefetch mode now defaults no OFF. To set
* prefetch mode OFF/ON use "hdparm -p8/-p9".
* Unmask irq is disabled when prefetch mode
* is enabled.
*
* Version 0.07 Trying to fix CD-ROM detection problem.
* "Prefetch" mode bit OFF for ide disks and
* ON for anything else.
*
*
* HT-6560B EIDE-controller support
* To activate controller support use kernel parameter "ide0=ht6560b".
* Use hdparm utility to enable PIO mode support.
*
* Author: Mikko Ala-Fossi <[EMAIL PROTECTED]>
* Jan Evert van Grootheest <[EMAIL PROTECTED]>
*
* Try: http://www.maf.iki.fi/~maf/ht6560b/
*/
#define HT6560B_VERSION "v0.07"
#undef REALLY_SLOW_IO /* most systems can safely undef this */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>
#include <linux/version.h>
#include <asm/io.h>
#include "ide_modes.h"
#define DEBUG /* remove comments for DEBUG messages */
/*
* The special i/o-port that HT-6560B uses to configuration:
* bit0 (0x01): "1" selects secondary interface
* bit2 (0x04): "1" enables FIFO function
* bit5 (0x20): "1" enables prefetched data read function (???)
*
* The special i/o-port that HT-6560A uses to configuration:
* bit0 (0x01): "0" selects secondary interface
* bit1 (0x02): "0" enables prefetched data read function
* bit2 (0x04): "0" enables multi-master system (?)
* bit3 (0x08): "1" 3 cycle time, "0" 2 cycle time (?)
*/
#define HT_CONFIG_PORT 0x3e6
#define HT_CONFIG(drivea) (byte)(((drivea)->drive_data & 0xff00) >> 8)
/*
* FIFO + PREFETCH (both a/b-model)
*/
#define HT_CONFIG_DEFAULT 0x1c /* no prefetch */
/* #define HT_CONFIG_DEFAULT 0x3c */ /* with prefetch */
#define HT_CONFIG_DEFAULT_A 0x0f /* no prefetch */
/* #define HT_CONFIG_DEFAULT_A 0x0d */ /* with prefetch */
#define HT_SECONDARY_IF 0x01
#define HT_PREFETCH_MODE 0x20
#define HT_PREFETCH_MODE_A 0x02
/*
* ht6560b Timing values:
*
* I reviewed some assembler source listings of htide drivers and found
* out how they setup those cycle time interfacing values, as they at Holtek
* call them. IDESETUP.COM that is supplied with the drivers figures out
* optimal values and fetches those values to drivers. I found out that
* they use IDE_SELECT_REG to fetch timings to the ide board right after
* interface switching. After that it was quite easy to add code to
* ht6560b.c.
*
* IDESETUP.COM gave me values 0x24, 0x45, 0xaa, 0xff that worked fine
* for hda and hdc. But hdb needed higher values to work, so I guess
* that sometimes it is necessary to give higher value than IDESETUP
* gives. [see cmd640.c for an extreme example of this. -ml]
*
* Perhaps I should explain something about these timing values:
* The higher nibble of value is the Recovery Time (rt) and the lower nibble
* of the value is the Active Time (at). Minimum value 2 is the fastest and
* the maximum value 15 is the slowest. Default values should be 15 for both.
* So 0x24 means 2 for rt and 4 for at. Each of the drives should have
* both values, and IDESETUP gives automatically rt=15 st=15 for CDROMs or
* similar. If value is too small there will be all sorts of failures.
*
* Timing byte consists of
* High nibble: Recovery Cycle Time (rt)
* The valid values range from 2 to 15. The default is 15.
*
* Low nibble: Active Cycle Time (at)
* The valid values range from 2 to 15. The default is 15.
*
* You can obtain optimized timing values by running Holtek IDESETUP.COM
* for DOS. DOS drivers get their timing values from command line, where
* the first value is the Recovery Time and the second value is the
* Active Time for each drive. Smaller value gives higher speed.
* In case of failures you should probably fall back to a higher value.
*/
#define HT_TIMING(drivea) (byte)((drivea)->drive_data & 0x00ff)
#define HT_TIMING_DEFAULT 0xff
#define HT_TIMING_DEFAULT_A 0xfe
/*
* This routine handles interface switching for the peculiar hardware design
* on the F.G.I./Holtek HT-6560B VLB IDE interface.
* The HT-6560B can only enable one IDE port at a time, and requires a
* silly sequence (below) whenever we switch between primary and secondary.
*/
static int ht_ver; /* chip found: 0 = HT-6560A, 1 = HT-6560B */
/*
* This routine is invoked from ide.c to prepare for access to a given drive.
*/
static void ht6560b_selectproc (ide_drive_t *drive)
{
unsigned long flags;
static byte current_select = 0;
static byte current_timing = 0;
byte select, timing;
__save_flags (flags); /* local CPU only */
__cli(); /* local CPU only */
select = HT_CONFIG(drive);
timing = HT_TIMING(drive);
if (select != current_select || timing != current_timing) {
current_select = select;
current_timing = timing;
if (ht_ver && (drive->media != ide_disk || !drive->present))
select |= HT_PREFETCH_MODE; /* for "B" only at present */
(void) inb(HT_CONFIG_PORT);
(void) inb(HT_CONFIG_PORT);
(void) inb(HT_CONFIG_PORT);
(void) inb(HT_CONFIG_PORT);
/*
* Set timing for this drive:
*/
outb(timing, IDE_SELECT_REG);
outb(select, HT_CONFIG_PORT);
if (!(ht_ver))
outb(0x00, IDE_CONTROL_REG); /* necessary! */
(void) inb(IDE_STATUS_REG);
#ifdef DEBUG
printk("ht6560b: %s: select=0x%02x timing=%#x\n", drive->name, select,
timing);
#endif
}
__restore_flags (flags); /* local CPU only */
}
static byte ht_pio2timings(ide_drive_t *drive, byte pio)
{
int active_time, recovery_time;
int active_cycles, recovery_cycles;
ide_pio_data_t d;
int bus_speed = system_bus_clock();
extern int ht_ver;
if (pio) {
pio = ide_get_best_pio_mode(drive, pio, 5, &d);
/*
* Just like opti621.c we try to calculate the
* actual cycle time for recovery and activity
* according system bus speed.
*/
active_time = ide_pio_timings[pio].active_time;
recovery_time = d.cycle_time
- active_time;
/* - ide_pio_timings[pio].setup_time; */
/* that's wrong, cycle time is active + recovery time */
/*
* Cycle times should be Vesa bus cycles
*/
active_cycles = (active_time * bus_speed + 999) / 1000;
recovery_cycles = (recovery_time * bus_speed + 999) / 1000;
/*
* Upper and lower limits
*/
if (active_cycles < 2) active_cycles = 2;
if (active_cycles > 15) active_cycles = 15;
if (ht_ver) { /* HT-6560B */
if (recovery_cycles < 2) recovery_cycles = 2;
if (recovery_cycles > 15) recovery_cycles = 0; /* 0==16 */
} else { /* HT-6560A */
if (recovery_cycles < 4) recovery_cycles = 4;
if (recovery_cycles == 16) recovery_cycles = 0; /* 0==16 */
if (recovery_cycles > 16) recovery_cycles = 1; /* 1==17 */
}
#ifdef DEBUG
printk("ht6560b: drive %s setting pio=%d recovery=%d (%dns) active=%d
(%dns)\n", drive->name, pio, recovery_cycles, recovery_time, active_cycles,
active_time);
#endif
return (byte)((recovery_cycles << 4) | active_cycles);
} else {
#ifdef DEBUG
printk("ht6560b: drive %s setting pio=0 (default timing)\n", drive->name);
#endif
return ht_ver ? HT_TIMING_DEFAULT : HT_TIMING_DEFAULT_A; /* default setting
*/
}
}
/*
* Enable/Disable so called prefetch mode
*/
static void ht_set_prefetch(ide_drive_t *drive, byte state)
{
unsigned long flags;
extern int ht_ver;
int t = ht_ver ? (HT_PREFETCH_MODE << 8) : (HT_PREFETCH_MODE_A << 8);
save_flags (flags); /* all CPUs */
cli(); /* all CPUs */
/*
* Prefetch mode and unmask irq seems to conflict
*/
if (state) {
if (ht_ver)
drive->drive_data |= t; /* enable prefetch mode */
else
drive->drive_data &= ~t;
drive->no_unmask = 1;
drive->unmask = 0;
} else {
if (ht_ver)
drive->drive_data &= ~t; /* disable prefetch mode */
else
drive->drive_data |= t;
drive->no_unmask = 0;
}
restore_flags (flags); /* all CPUs */
#ifdef DEBUG
printk("ht6560b: drive %s prefetch mode %sabled\n", drive->name, (state ? "en" :
"dis"));
#endif
}
static void tune_ht6560b (ide_drive_t *drive, byte pio)
{
unsigned long flags;
byte timing;
switch (pio) {
case 8: /* set prefetch off */
case 9: /* set prefetch on */
ht_set_prefetch(drive, pio & 1);
return;
}
timing = ht_pio2timings(drive, pio);
save_flags (flags); /* all CPUs */
cli(); /* all CPUs */
drive->drive_data &= 0xff00;
drive->drive_data |= timing;
restore_flags (flags); /* all CPUs */
#ifdef DEBUG
printk("ht6560b: drive %s tuned to pio mode %d timing=%#x\n", drive->name, pio,
timing);
#endif
}
/*
* Autodetection and initialization of ht6560b
*/
static int __init try_to_init_ht6560b(void)
{
byte orig_value;
int i, t, index;
extern int ht_ver;
printk("ht6560b: try_to_init started\n");
/* Autodetect ht6560b */
if ((orig_value=inb(HT_CONFIG_PORT)) == 0xff) /* no chip */
return 0;
printk("ht6560b: try_to_init checkpoint 1\n");
for (i=3;i>0;i--) {
outb(0x00, HT_CONFIG_PORT);
if (!(inb(HT_CONFIG_PORT))) {
outb(orig_value, HT_CONFIG_PORT);
return 0;
}
}
/* if (!( (~inb(HT_CONFIG_PORT)) & 0x3f )) {
outb(orig_value, HT_CONFIG_PORT);
return 0;
}
*/
/* this is from ht6560b DOS driver and I don't think it is correct */
/* My opinion is that shall be checked that the first 3 writes */
/* don't write the registre, i.e. it is read-only and non-zero */
printk("ht6560b: try_to_init checkpoint 2\n");
outb(0x00, HT_CONFIG_PORT);
if ((~inb(HT_CONFIG_PORT))& 0x3f) {
if ((inb(HT_CONFIG_PORT))) {
outb(orig_value, HT_CONFIG_PORT);
return 0;
}
ht_ver = 0; /* HT-6560A */
index = ~orig_value & 0x01;
outb(HT_CONFIG_DEFAULT_A & ~index, HT_CONFIG_PORT);
outb(HT_TIMING_DEFAULT_A, index ? 0x176 : 0x1f6); /* IDE_SELECT_REG */
ide_hwifs[index].chipset = ide_ht6560b; /* ide_ht6560a */
ide_hwifs[index].selectproc = &ht6560b_selectproc;
ide_hwifs[index].tuneproc = &tune_ht6560b;
/*
* Setting default configurations for drives
*/
t = (HT_CONFIG_DEFAULT_A << 8);
t |= HT_TIMING_DEFAULT_A;
t &= ~(index << 8);
ide_hwifs[index].drives[0].drive_data =
ide_hwifs[index].drives[1].drive_data = t;
} else {
ht_ver = 1; /* HT-6560B */
outb(HT_CONFIG_DEFAULT, HT_CONFIG_PORT);
outb(HT_TIMING_DEFAULT, 0x1f6); /* IDE_SELECT_REG */
ide_hwifs[0].chipset =
ide_hwifs[1].chipset = ide_ht6560b;
ide_hwifs[0].selectproc =
ide_hwifs[1].selectproc = &ht6560b_selectproc;
ide_hwifs[0].tuneproc =
ide_hwifs[1].tuneproc = &tune_ht6560b;
ide_hwifs[0].serialized = /* is this needed? */
ide_hwifs[1].serialized = 1; /* is this needed? */
ide_hwifs[0].mate = &ide_hwifs[1];
ide_hwifs[1].mate = &ide_hwifs[0];
ide_hwifs[1].channel = 1;
/*
* Setting default configurations for drives
*/
t = (HT_CONFIG_DEFAULT << 8);
t |= HT_TIMING_DEFAULT;
ide_hwifs[0].drives[0].drive_data =
ide_hwifs[0].drives[1].drive_data = t;
t |= (HT_SECONDARY_IF << 8);
ide_hwifs[1].drives[0].drive_data =
ide_hwifs[1].drives[1].drive_data = t;
}
(void) inb(0x1f7); /* IDE_STATUS_REG */
printk("\nht6560b " HT6560B_VERSION
": HT6560%c chip detected and initialized"
#ifdef DEBUG
" with debug enabled"
#endif
, ht_ver ? 'B' : 'A' );
return 1;
}
void __init init_ht6560b (void)
{
printk("ht6560b: init procedure called\n");
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0)
if (check_region(0x3e6, 1)) {
printk(KERN_ERR "ht6560b: PORT 0x3E6 ALREADY IN USE\n");
return;
}
#endif
if (try_to_init_ht6560b())
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0)
request_region(0x3e6, 1, "ht6560b")
#endif
;
else
printk(KERN_ERR "ht6560b: HT-6560A/B chip not found\n");
}
/*
* linux/drivers/ide/qd65xx.c Version 0.06 Aug 3, 2000
*
* Copyright (C) 1996-2000 Linus Torvalds & author (see below)
*/
/*
* Version 0.03 Cleaned auto-tune, added probe
* Version 0.04 Added second channel tuning
* Version 0.05 Enhanced tuning ; added qd6500 support
* Version 0.06 added dos driver's list
*
* QDI QD6500/QD6580 EIDE controller fast support
*
* Please set local bus speed using kernel parameter idebus
* for example, "idebus=33" stands for 33Mhz VLbus
* To activate controller support, use "ide0=qd65xx"
* To enable tuning, use "ide0=autotune"
* To enable second channel tuning (qd6580 only), use "ide1=autotune"
*/
/*
* Rewritten from the work of Colten Edwards <[EMAIL PROTECTED]> by
* Samuel Thibault <[EMAIL PROTECTED]>
*/
#undef REALLY_SLOW_IO /* most systems can safely undef this */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>
#include <asm/io.h>
#include "ide_modes.h"
#include "qd65xx.h"
/*
* I/O ports are 0x30-0x31 (and 0x32-0x33 for qd6580)
* or 0xb0-0xb1 (and 0xb2-0xb3 for qd6580)
* -- qd6500 is a single IDE interface
* -- qd6580 is a dual IDE interface
*
* More research on qd6580 being done by [EMAIL PROTECTED] (David)
* More Information given by Petr Soucek ([EMAIL PROTECTED])
* http://www.ryston.cz/petr/vlb
*/
/*
* base: Timer1
*
*
* base+0x01: Config (R/O)
*
* bit 0: ide baseport: 1 = 0x1f0 ; 0 = 0x170 (only useful for qd6500)
* bit 1: qd65xx baseport: 1 = 0xb0 ; 0 = 0x30
* bit 2: ID3: bus speed: 1 = <=33MHz ; 0 = >33MHz
* bit 3: qd6500: 1 = disabled, 0 = enabled
* qd6580: 1
* upper nibble:
* qd6500: 1100
* qd6580: either 1010 or 0101
*
* base+0x02: Timer2 (qd6580 only)
*
*
* base+0x03: Control (qd6580 only)
*
* bits 0-3 must always be set 1
* bit 4 must be set 1, but is set 0 by dos driver while measuring vlb clock
* bit 0 : 1 = Only primary port enabled : channel 0 for hda, channel 1 for hdb
* 0 = Primary and Secondary ports enabled : channel 0 for hda & hdb
* channel 1 for hdc & hdd
* bit 1 : 1 = only disks on primary port
* 0 = disks & ATAPI devices on primary port
* bit 2-4 : always 0
* bit 5 : status, but of what ?
* bit 6 : always set 1 by dos driver
* bit 7 : set 1 for non-ATAPI devices on primary port
* (maybe read-ahead and post-write buffer ?)
*/
static int timings[4]={-1,-1,-1,-1}; /* stores current timing for each timer */
static void qd_write_reg (byte content, byte reg)
{
unsigned long flags;
save_flags(flags); /* all CPUs */
cli(); /* all CPUs */
outb(content,reg);
restore_flags(flags); /* all CPUs */
}
byte __init qd_read_reg (byte reg)
{
unsigned long flags;
byte read;
save_flags(flags); /* all CPUs */
cli(); /* all CPUs */
read = inb(reg);
restore_flags(flags); /* all CPUs */
return read;
}
/*
* qd_select:
*
* This routine is invoked from ide.c to prepare for access to a given drive.
*/
static void qd_select (ide_drive_t *drive)
{
byte index = (( (QD_TIMREG(drive)) & 0x80 ) >> 7) |
(QD_TIMREG(drive) & 0x02);
if (timings[index] != QD_TIMING(drive))
qd_write_reg(timings[index] = QD_TIMING(drive), QD_TIMREG(drive));
}
/*
* qd6500_compute_timing
*
* computes the timing value where
* lower nibble represents active time, in count of VLB clocks
* upper nibble represents recovery time, in count of VLB clocks
*/
static byte qd6500_compute_timing (ide_hwif_t *hwif, int active_time, int
recovery_time)
{
byte active_cycle,recovery_cycle;
if (system_bus_clock()<=33) {
active_cycle = 9 - IDE_IN(active_time * system_bus_clock() / 1000
+ 1, 2, 9);
recovery_cycle = 15 - IDE_IN(recovery_time * system_bus_clock() / 1000
+ 1, 0, 15);
} else {
active_cycle = 8 - IDE_IN(active_time * system_bus_clock() / 1000
+ 1, 1, 8);
recovery_cycle = 18 - IDE_IN(recovery_time * system_bus_clock() / 1000
+ 1, 3, 18);
}
return((recovery_cycle<<4) | 0x08 | active_cycle);
}
/*
* qd6580_compute_timing
*
* idem for qd6580
*/
static byte qd6580_compute_timing (int active_time, int recovery_time)
{
byte active_cycle = 17-IDE_IN(active_time * system_bus_clock() / 1000 + 1,
2, 17);
byte recovery_cycle = 15-IDE_IN(recovery_time * system_bus_clock() / 1000 + 1,
2, 15);
return((recovery_cycle<<4) | active_cycle);
}
/*
* qd_find_disk_type
*
* tries to find timing from dos driver's table
*/
static int qd_find_disk_type (ide_drive_t *drive,
int *active_time, int *recovery_time)
{
struct qd65xx_timing_s *p;
char model[40];
if (!*drive->id->model) return 0;
strncpy(model,drive->id->model,40);
ide_fixstring(model,40,1); /* byte-swap */
for (p = qd65xx_timing ; p->offset != -1 ; p++) {
if (!strncmp(p->model, model+p->offset,4)) {
printk(KERN_DEBUG "%s: listed !\n",drive->name);
*active_time = p->active;
*recovery_time = p->recovery;
return 1;
}
}
return 0;
}
/*
* qd_timing_ok:
*
* check whether timings don't conflict
*/
static int qd_timing_ok (ide_drive_t drives[])
{
return (IDE_IMPLY(drives[0].present && drives[1].present,
IDE_IMPLY(QD_TIMREG(drives) == QD_TIMREG(drives+1),
QD_TIMING(drives) == QD_TIMING(drives+1))));
/* if same timing register, must be same timing */
}
/*
* qd_set_timing:
*
* records the timing, and enables selectproc as needed
*/
static void qd_set_timing (ide_drive_t *drive, byte timing)
{
ide_hwif_t *hwif = HWIF(drive);
drive->drive_data &= 0xff00;
drive->drive_data |= timing;
if (qd_timing_ok(hwif->drives)) {
qd_select(drive); /* selects once */
hwif->selectproc = NULL;
} else
hwif->selectproc = &qd_select;
printk(KERN_DEBUG "%s: %#x\n",drive->name,timing);
}
/*
* qd6500_tune_drive
*/
static void qd6500_tune_drive (ide_drive_t *drive, byte pio)
{
int active_time = 175;
int recovery_time = 415; /* worst case values from the dos driver */
if (drive->id && !qd_find_disk_type(drive,&active_time,&recovery_time)
&& drive->id->tPIO && (drive->id->field_valid & 0x02)
&& drive->id->eide_pio >= 240) {
printk(KERN_INFO "%s: PIO mode%d\n", drive->name,
drive->id->tPIO);
active_time = 110;
recovery_time = drive->id->eide_pio - 120;
}
qd_set_timing(drive,qd6500_compute_timing(HWIF(drive),active_time,recovery_time));
}
/*
* qd6580_tune_drive
*/
static void qd6580_tune_drive (ide_drive_t *drive, byte pio)
{
ide_pio_data_t d;
int base = HWIF(drive)->select_data;
int active_time = 175;
int recovery_time = 415; /* worst case values from the dos driver */
if (drive->id && !qd_find_disk_type(drive,&active_time,&recovery_time)) {
pio = ide_get_best_pio_mode(drive, pio, 255, &d);
pio = IDE_MIN(pio,4);
switch (pio) {
case 0: break;
case 3:
if (d.cycle_time >= 110) {
active_time = 86;
recovery_time = d.cycle_time-102;
} else
printk(KERN_WARNING "%s: Strange recovery time
!\n",drive->name);
break;
case 4:
if (d.cycle_time >= 69) {
active_time = 70;
recovery_time = d.cycle_time-61;
} else
printk(KERN_WARNING "%s: Strange recovery time
!\n",drive->name);
break;
default:
if (d.cycle_time >= 180) {
active_time = 110;
recovery_time = d.cycle_time - 120;
} else {
active_time =
ide_pio_timings[pio].active_time;
recovery_time = d.cycle_time
-active_time;
}
}
printk(KERN_INFO "%s: PIO mode%d\n",drive->name,pio);
}
if (!HWIF(drive)->channel && drive->media != ide_disk) {
qd_write_reg(0x5f,QD_CONTROL_PORT);
printk(KERN_WARNING "%s: ATAPI: disabled read-ahead FIFO and
post-write buffer on %s.\n",drive->name,HWIF(drive)->name);
}
qd_set_timing(drive,qd6580_compute_timing(active_time,recovery_time));
}
/*
* qd_testreg
*
* tests if the given port is a register
*/
static int __init qd_testreg(int port)
{
byte savereg;
byte readreg;
unsigned long flags;
save_flags(flags); /* all CPUs */
cli(); /* all CPUs */
savereg = inb_p(port);
outb_p(QD_TESTVAL,port); /* safe value */
readreg = inb_p(port);
outb(savereg,port);
restore_flags(flags); /* all CPUs */
if (savereg == QD_TESTVAL) {
printk(KERN_ERR "Outch ! the probe for qd65xx isn't reliable !\n");
printk(KERN_ERR "Please contact maintainers to tell about your
hardware\n");
printk(KERN_ERR "Assuming qd65xx is not present.\n");
return 1;
}
return (readreg != QD_TESTVAL);
}
/*
* probe:
*
* looks at the specified baseport, and if qd found, registers & initialises it
* return 1 if another qd may be probed
*/
int __init probe (int base)
{
byte config;
byte index;
config = qd_read_reg(QD_CONFIG_PORT);
if (! ((config & QD_CONFIG_BASEPORT) >> 1 == (base == 0xb0)) ) return 1;
index = ! (config & QD_CONFIG_IDE_BASEPORT);
if ((config & 0xf0) == QD_CONFIG_QD6500) {
ide_hwif_t *hwif = &ide_hwifs[index];
if (qd_testreg(base)) return 1; /* bad register */
/* qd6500 found */
printk(KERN_NOTICE "%s: qd6500 at %#x\n",
ide_hwifs[index].name, base);
printk(KERN_DEBUG "qd6500: config=%#x\n, ID3=%u\n",
config, QD_ID3);
if (config & QD_CONFIG_DISABLED) {
printk(KERN_WARNING "qd6500 is disabled !\n");
return 1;
}
hwif->chipset = ide_qd65xx;
hwif->select_data = base;
hwif->config_data = config;
hwif->drives[0].drive_data =
hwif->drives[1].drive_data = QD6500_DEF_DATA;
hwif->drives[0].io_32bit =
hwif->drives[1].io_32bit = 1;
hwif->tuneproc = &qd6500_tune_drive;
return 1;
}
if (((config & 0xf0) == QD_CONFIG_QD6580_A) || ((config & 0xf0) ==
QD_CONFIG_QD6580_B)) {
byte control;
if (qd_testreg(base) || qd_testreg(base+0x02)) return 1;
/* bad registers */
/* qd6580 found */
control = qd_read_reg(QD_CONTROL_PORT);
printk(KERN_NOTICE "qd6580 at %#x\n", base);
printk(KERN_DEBUG "qd6580: config=%#x, control=%#x, ID3=%u\n",
config, control, QD_ID3);
if (control & QD_CONTR_SEC_DISABLED) {
ide_hwif_t *hwif = &ide_hwifs[index];
/* secondary disabled */
printk(KERN_INFO "%s: qd6580: single IDE board\n",
ide_hwifs[index].name);
hwif->chipset = ide_qd65xx;
hwif->select_data = base;
hwif->config_data = config | (control <<8);
hwif->drives[0].drive_data =
hwif->drives[1].drive_data = QD6580_DEF_DATA;
hwif->drives[0].io_32bit =
hwif->drives[1].io_32bit = 1;
hwif->tuneproc = &qd6580_tune_drive;
qd_write_reg(QD_DEF_CONTR,QD_CONTROL_PORT);
return 1;
} else {
int i,j;
/* secondary enabled */
printk(KERN_INFO "%s&%s: qd6580: dual IDE board\n",
ide_hwifs[0].name,ide_hwifs[1].name);
for (i=0;i<2;i++) {
ide_hwifs[i].chipset = ide_qd65xx;
ide_hwifs[i].mate = &ide_hwifs[i^1];
ide_hwifs[i].channel = i;
ide_hwifs[i].select_data = base;
ide_hwifs[i].config_data = config | (control <<8);
ide_hwifs[i].tuneproc = &qd6580_tune_drive;
for (j=0;j<2;j++) {
ide_hwifs[i].drives[j].drive_data =
QD6580_DEF_DATA;
ide_hwifs[i].drives[j].io_32bit = 1;
}
}
qd_write_reg(QD_DEF_CONTR,QD_CONTROL_PORT);
return 0; /* no other qd65xx possible */
}
}
/* no qd65xx found */
return 1;
}
/*
* init_qd65xx:
*
* called at the very beginning of initialization ; should just probe and link
*/
void __init init_qd65xx (void)
{
if (probe(0x30)) probe(0xb0);
}
/*
* linux/drivers/ide/qd65xx.h
*
* Copyright (c) 2000 Linus Torvalds & authors
*/
/*
* Authors: Petr Soucek <[EMAIL PROTECTED]>
* Samuel Thibault <[EMAIL PROTECTED]>
*/
/* truncates a in [b,c] */
#define IDE_IN(a,b,c) ( ((a)<(b)) ? (b) : ( (a)>(c) ? (c) : (a)) )
#define IDE_IMPLY(a,b) ((!(a)) || (b))
#define QD_TIM1_PORT (base)
#define QD_CONFIG_PORT (base+0x01)
#define QD_TIM2_PORT (base+0x02)
#define QD_CONTROL_PORT (base+0x03)
#define QD_CONFIG_IDE_BASEPORT 0x01
#define QD_CONFIG_BASEPORT 0x02
#define QD_CONFIG_ID3 0x04
#define QD_CONFIG_DISABLED 0x08
#define QD_CONFIG_QD6500 0xc0
#define QD_CONFIG_QD6580_A 0xa0
#define QD_CONFIG_QD6580_B 0x50
#define QD_CONTR_SEC_DISABLED 0x01
#define QD_ID3 (config & QD_CONFIG_ID3)
#define QD_CONFIG(hwif) ((hwif)->config_data & 0x00ff)
#define QD_CONTROL(hwif) (((hwif)->config_data & 0xff00) >> 8)
#define QD_TIMING(drive) (byte)(((drive)->drive_data) & 0x00ff)
#define QD_TIMREG(drive) (byte)((((drive)->drive_data) & 0xff00) >> 8)
#define QD6500_DEF_DATA ((QD_TIM1_PORT<<8) | (QD_ID3 ? 0x0c : 0x08))
#define QD6580_DEF_DATA ((QD_TIM1_PORT<<8) | (QD_ID3 ? 0x0a : 0x00))
#define QD_DEF_CONTR (0x40 | ((control & 0x02) ? 0x9f : 0x1f))
#define QD_TESTVAL 0x19 /* safe value */
/* Drive specific timing taken from DOS driver v3.7 */
struct qd65xx_timing_s {
char offset; /* ofset from the beginning of Model Number" */
char model[4]; /* 4 chars from Model number, no conversion */
short active; /* active time */
short recovery; /* recovery time */
} qd65xx_timing [] = {
{ 30, "2040", 110, 225 }, /* Conner CP30204 */
{ 30, "2045", 135, 225 }, /* Conner CP30254 */
{ 30, "1040", 155, 325 }, /* Conner CP30104 */
{ 30, "1047", 135, 265 }, /* Conner CP30174 */
{ 30, "5344", 135, 225 }, /* Conner CP3544 */
{ 30, "01 4", 175, 405 }, /* Conner CP-3104 */
{ 27, "C030", 175, 375 }, /* Conner CP3000 */
{ 8, "PL42", 110, 295 }, /* Quantum LP240 */
{ 8, "PL21", 110, 315 }, /* Quantum LP120 */
{ 8, "PL25", 175, 385 }, /* Quantum LP52 */
{ 4, "PA24", 110, 285 }, /* WD Piranha SP4200 */
{ 6, "2200", 110, 260 }, /* WD Caviar AC2200 */
{ 6, "3204", 110, 235 }, /* WD Caviar AC2340 */
{ 6, "1202", 110, 265 }, /* WD Caviar AC2120 */
{ 0, "DS3-", 135, 315 }, /* Teac SD340 */
{ 8, "KM32", 175, 355 }, /* Toshiba MK234 */
{ 2, "53A1", 175, 355 }, /* Seagate ST351A */
{ 2, "4108", 175, 295 }, /* Seagate ST1480A */
{ 2, "1344", 175, 335 }, /* Seagate ST3144A */
{ 6, "7 12", 110, 225 }, /* Maxtor 7213A */
{ 30, "02F4", 145, 295 }, /* Conner 3204F */
{ 2, "1302", 175, 335 }, /* Seagate ST3120A */
{ 2, "2334", 145, 265 }, /* Seagate ST3243A */
{ 2, "2338", 145, 275 }, /* Seagate ST3283A */
{ 2, "3309", 145, 275 }, /* Seagate ST3390A */
{ 2, "5305", 145, 275 }, /* Seagate ST3550A */
{ 2, "4100", 175, 295 }, /* Seagate ST1400A */
{ 2, "4110", 175, 295 }, /* Seagate ST1401A */
{ 2, "6300", 135, 265 }, /* Seagate ST3600A */
{ 2, "5300", 135, 265 }, /* Seagate ST3500A */
{ 6, "7 31", 135, 225 }, /* Maxtor 7131 AT */
{ 6, "7 43", 115, 265 }, /* Maxtor 7345 AT */
{ 6, "7 42", 110, 255 }, /* Maxtor 7245 AT */
{ 6, "3 04", 135, 265 }, /* Maxtor 340 AT */
{ 6, "61 0", 135, 285 }, /* WD AC160 */
{ 6, "1107", 135, 235 }, /* WD AC1170 */
{ 6, "2101", 110, 220 }, /* WD AC1210 */
{ 6, "4202", 135, 245 }, /* WD AC2420 */
{ 6, "41 0", 175, 355 }, /* WD Caviar 140 */
{ 6, "82 0", 175, 355 }, /* WD Caviar 280 */
{ 8, "PL01", 175, 375 }, /* Quantum LP105 */
{ 8, "PL25", 110, 295 }, /* Quantum LP525 */
{ 10, "4S 2", 175, 385 }, /* Quantum ELS42 */
{ 10, "8S 5", 175, 385 }, /* Quantum ELS85 */
{ 10, "1S72", 175, 385 }, /* Quantum ELS127 */
{ 10, "1S07", 175, 385 }, /* Quantum ELS170 */
{ 8, "ZE42", 135, 295 }, /* Quantum EZ240 */
{ 8, "ZE21", 175, 385 }, /* Quantum EZ127 */
{ 8, "ZE58", 175, 385 }, /* Quantum EZ85 */
{ 8, "ZE24", 175, 385 }, /* Quantum EZ42 */
{ 27, "C036", 155, 325 }, /* Conner CP30064 */
{ 27, "C038", 155, 325 }, /* Conner CP30084 */
{ 6, "2205", 110, 255 }, /* WDC AC2250 */
{ 2, " CHA", 140, 415 }, /* WDC AH series; WDC AH260, WDC */
{ 2, " CLA", 140, 415 }, /* WDC AL series: WDC AL2120, 2170, */
{ 4, "UC41", 140, 415 }, /* WDC CU140 */
{ 6, "1207", 130, 275 }, /* WDC AC2170 */
{ 6, "2107", 130, 275 }, /* WDC AC1270 */
{ 6, "5204", 130, 275 }, /* WDC AC2540 */
{ 30, "3004", 110, 235 }, /* Conner CP30340 */
{ 30, "0345", 135, 255 }, /* Conner CP30544 */
{ 12, "12A3", 175, 320 }, /* MAXTOR LXT-213A */
{ 12, "43A0", 145, 240 }, /* MAXTOR LXT-340A */
{ 6, "7 21", 180, 290 }, /* Maxtor 7120 AT */
{ 6, "7 71", 135, 240 }, /* Maxtor 7170 AT */
{ 12, "45\0000", 110, 205 }, /* MAXTOR MXT-540 */
{ 8, "PL11", 180, 290 }, /* QUANTUM LP110A */
{ 8, "OG21", 150, 275 }, /* QUANTUM GO120 */
{ 12, "42A5", 175, 320 }, /* MAXTOR LXT-245A */
{ 2, "2309", 175, 295 }, /* ST3290A */
{ 2, "3358", 180, 310 }, /* ST3385A */
{ 2, "6355", 180, 310 }, /* ST3655A */
{ 2, "1900", 175, 270 }, /* ST9100A */
{ 2, "1954", 175, 270 }, /* ST9145A */
{ 2, "1909", 175, 270 }, /* ST9190AG */
{ 2, "2953", 175, 270 }, /* ST9235A */
{ 2, "1359", 175, 270 }, /* ST3195A */
{ 24, "3R11", 175, 290 }, /* ALPS ELECTRIC Co.,LTD, DR311C */
{ 0, "2M26", 175, 215 }, /* M262XT-0Ah */
{ 4, "2253", 175, 300 }, /* HP C2235A */
{ 4, "-32A", 145, 245 }, /* H3133-A2 */
{ 30, "0326", 150, 270 }, /* Samsung Electronics 120MB */
{ 30, "3044", 110, 195 }, /* Conner CFA340A */
{ 30, "43A0", 110, 195 }, /* Conner CFA340A */
{ -1, " ", 175, 415 } /* unknown disk name */
};
