Marek Vasut <ma...@denx.de> writes: >> Isn't there the case of a single NAND controller with 2 identical chips, >> each a 8 bit NAND chip, and the controller aggregating them to offer the >> OS a single 16-bit NAND chip ? > > Is that using 1 or 2 physical chipselect lines on the CPU (controller) ? I think it's 2 physical chipselects (CS0 and CS1). The way I understand it is that the NAND controller asserts them both, issues the command on the command line (shared between the 2 chips), and reads/writes on the separate data lines.
Cheers. -- Robert -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
