On Tue, 17 May 2016, Paul Burton wrote:
> This series fixes a few small issues with support for External Interrupt
> Controllers (cpu_has_veic), ensuring that it is configured to service
> all interrupts by default & that when a GIC is present it's enabled when
> expected.
>
> Applies atop v4.6.
>
> Paul Burton (3):
> MIPS: Clear Status IPL field when using EIC
> MIPS: smp-cps: Clear Status IPL field when using EIC
> irqchip: mips-gic: Setup EIC mode on each CPU if it's in use
I was not on CC for patch 1/3 and I assume this should go through one
tree. Ralf, can you pick that up with my acked-by for the irqchip change?
Thanks,
tglx
