Verification failed on Tegra. Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR register as on Tegra bit-6 is used for internal usage to know if FIFO mode is enabled. while (1) { iir = tegra_uart_read(tup, UART_IIR); +iir &= UART_IIR_MASK;
Thanks, Shardar -----Original Message----- From: Laxman Dewangan Sent: Thursday, March 30, 2017 3:48 PM To: Olliver Schinagl <oli...@schinagl.nl>; Greg Kroah-Hartman <gre...@linuxfoundation.org>; Jiri Slaby <jsl...@suse.com>; Stephen Warren <swar...@wwwdotorg.org>; Thierry Reding <thierry.red...@gmail.com>; Alexandre Courbot <gnu...@gmail.com> Cc: linux-ser...@vger.kernel.org; linux-te...@vger.kernel.org; linux-kernel@vger.kernel.org; Shardar Mohammed <smoham...@nvidia.com> Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote: > The tegra serial IP seems to be following the common layout and the > interrupt ID's match up nicely. Replace the magic values to match the > common serial_reg defines, with the addition of the Tegra unique End > of Data interrupt. > > Signed-off-by: Olliver Schinagl <oli...@schinagl.nl> > --- Adding Shardar for verifications. Acked-by: Laxman Dewangan <ldewan...@nvidia.com>