On Sat, Jan 20, 2018 at 12:03:31PM +0000, David Woodhouse wrote: > AMD doesn't implement the Speculation Control MSR that Intel does, but > the Prediction Control MSR does exist and is advertised by a separate > CPUID bit. Add support for that. > > Signed-off-by: David Woodhouse <d...@amazon.co.uk> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/cpu/scattered.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h > b/arch/x86/include/asm/cpufeatures.h > index adebdaa..624d978 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -207,6 +207,7 @@ > #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation > for Spectre variant 2 */ > #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor > Inventory Number */ > > +#define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR > (AMD) */
Right, so this bit I've seen being called differently. Tom, can you clarify pls? Also, public ZN PPR says about it: CPUID_Fn80000007_EDX [Advanced Power Management Information] (ApmInfoEdx) ... 12 ApmPwrReporting: APM power reporting. Read-only. Reset: Fixed,0. so I'm guessing it has been repurposed or so as APM is not used anymore? Leaving in the rest for reference. > #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth > Allocation */ > #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on > context switches */ > > diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c > index df11f5d..c76009e 100644 > --- a/arch/x86/kernel/cpu/scattered.c > +++ b/arch/x86/kernel/cpu/scattered.c > @@ -28,6 +28,7 @@ static const struct cpuid_bit cpuid_bits[] = { > { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, > { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, > { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, > + { X86_FEATURE_AMD_PRED_CMD, CPUID_EDX, 12, 0x80000007, 0 }, > { X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 }, > { 0, 0, 0, 0, 0 } > }; > -- > 2.7.4 > -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.