> On Sat, Jan 20, 2018 at 12:03:31PM +0000, David Woodhouse wrote: >> AMD doesn't implement the Speculation Control MSR that Intel does, but >> the Prediction Control MSR does exist and is advertised by a separate >> CPUID bit. Add support for that. >> >> Signed-off-by: David Woodhouse <d...@amazon.co.uk> >> --- >> arch/x86/include/asm/cpufeatures.h | 1 + >> arch/x86/kernel/cpu/scattered.c | 1 + >> 2 files changed, 2 insertions(+) >> >> diff --git a/arch/x86/include/asm/cpufeatures.h >> b/arch/x86/include/asm/cpufeatures.h >> index adebdaa..624d978 100644 >> --- a/arch/x86/include/asm/cpufeatures.h >> +++ b/arch/x86/include/asm/cpufeatures.h >> @@ -207,6 +207,7 @@ >> #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline >> mitigation for Spectre variant 2 */ >> #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor >> Inventory >> Number */ >> >> +#define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR >> (AMD) */ > > Right, so this bit I've seen being called differently. Tom, can you > clarify pls?
Yeah, that's fat-fingered in a cut/paste in refactoring. Fixed in what I posted this morning. I would like to see public docs with it though... Tom? -- dwmw2