On 1/21/2018 6:22 AM, David Woodhouse wrote: > >> On Sat, Jan 20, 2018 at 12:03:31PM +0000, David Woodhouse wrote: >>> AMD doesn't implement the Speculation Control MSR that Intel does, but >>> the Prediction Control MSR does exist and is advertised by a separate >>> CPUID bit. Add support for that. >>> >>> Signed-off-by: David Woodhouse <d...@amazon.co.uk> >>> --- >>> arch/x86/include/asm/cpufeatures.h | 1 + >>> arch/x86/kernel/cpu/scattered.c | 1 + >>> 2 files changed, 2 insertions(+) >>> >>> diff --git a/arch/x86/include/asm/cpufeatures.h >>> b/arch/x86/include/asm/cpufeatures.h >>> index adebdaa..624d978 100644 >>> --- a/arch/x86/include/asm/cpufeatures.h >>> +++ b/arch/x86/include/asm/cpufeatures.h >>> @@ -207,6 +207,7 @@ >>> #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline >>> mitigation for Spectre variant 2 */ >>> #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor >>> Inventory >>> Number */ >>> >>> +#define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR >>> (AMD) */
You should use the existing 0x80000008 EBX entry for this. >> >> Right, so this bit I've seen being called differently. Tom, can you >> clarify pls? > > Yeah, that's fat-fingered in a cut/paste in refactoring. Fixed in what I > posted this morning. I would like to see public docs with it though... > Tom? I'm looking to see if we have our specification posted on a public link. But, in the meantime, AMD will advertise all three features (IBRS, IBPB and STIBP) in separate CPUID bits: IBPB: 0x80000008 EBX[12] IBRS: 0x80000008 EBX[14] STIBP: 0x80000008 EBX[15] And we will follow the Intel specification should we set the bits in CPUID 0x7. For example, IBPB support would be indicated by CPUID: 0x80000008 EBX[12] || 0x7 EDX[26] Thanks, Tom >
