+ Tom.
On Thu, Jan 25, 2018 at 04:14:11PM +0000, David Woodhouse wrote:
> AMD exposes the PRED_CMD/SPEC_CTRL MSRs slightly differently to Intel.
> See http://lkml.kernel.org/r/[email protected]
>
> Signed-off-by: David Woodhouse <[email protected]>
> Reviewed-by: Greg Kroah-Hartman <[email protected]>
> ---
> arch/x86/include/asm/cpufeatures.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include/asm/cpufeatures.h
> index 0a51070..ae3212f 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -269,6 +269,9 @@
> #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
> #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired
> Count */
> #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always
> save/restore FP error pointers */
> +#define X86_FEATURE_AMD_PRED_CMD (13*32+12) /* Prediction Command MSR
> (AMD) */
> +#define X86_FEATURE_AMD_SPEC_CTRL (13*32+14) /* Speculation Control MSR
> only (AMD) */
> +#define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread
> Indirect Branch Predictors (AMD) */
So this leaf is AMD-specific so you can drop the AMD strings above.
Also, let's simplify this as those flags appear in /proc/cpuinfo:
#define X86_FEATURE_IBPB (13*32+12) /* Indirect Branch
Prediction Barrier: Prediction Command MSR */
#define X86_FEATURE_IBRS (13*32+14) /* Speculation Control MSR
only */
#define X86_FEATURE_STIBP (13*32+15) /* Single Thread Indirect
Branch Predictors */
so that we have "ibpb", "ibrs" and "stibp" respectively.
Thx.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
