On Fri, Jan 26, 2018 at 03:06:20PM -0600, Tom Lendacky wrote:
> So I like the idea of AMD_IBRS/AMD_IBPB/AMD_STIBP and then use the magic
> quotes as appropriate. We could probably use the magic quotes on
> AMD_STIBP and set X86_FEATURE_STIBP when we see X86_FEATURE_AMD_STIBP.
Like this?
We set the respective Intel features when we detect the AMD ones so that
we get correct /proc/cpuinfo strings. The respective AMD ones are not
shown.
---
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86/include/asm/cpufeatures.h
index 40f92eff09df..73080d5a5696 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -272,9 +272,9 @@
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired
Count */
#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP
error pointers */
-#define X86_FEATURE_AMD_PRED_CMD (13*32+12) /* Prediction Command MSR
(AMD) */
-#define X86_FEATURE_AMD_SPEC_CTRL (13*32+14) /* Speculation Control MSR
only (AMD) */
-#define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect
Branch Predictors (AMD) */
+#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch
Prediction Barrier MSR */
+#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Speculation Control
MSR only */
+#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect
Branch Predictors */
/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index ea831c858195..14c8a7869450 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -872,6 +872,12 @@ static void init_amd(struct cpuinfo_x86 *c)
/* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
if (!cpu_has(c, X86_FEATURE_XENPV))
set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
+
+ if (cpu_has(c, X86_FEATURE_AMD_IBRS))
+ set_cpu_cap(c, X86_FEATURE_IBRS);
+
+ if (cpu_has(c, X86_FEATURE_AMD_STIBP))
+ set_cpu_cap(c, X86_FEATURE_STIBP);
}
#ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index c988a8acb0d5..be068aea6bda 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -266,7 +266,7 @@ static void __init spectre_v2_select_mitigation(void)
/* Initialize Indirect Branch Prediction Barrier if supported */
if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) ||
- boot_cpu_has(X86_FEATURE_AMD_PRED_CMD)) {
+ boot_cpu_has(X86_FEATURE_AMD_IBPB)) {
setup_force_cpu_cap(X86_FEATURE_IBPB);
pr_info("Enabling Indirect Branch Prediction Barrier\n");
}
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 7a3d216875fc..571249b8bc00 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -177,14 +177,14 @@ static void early_init_intel(struct cpuinfo_x86 *c)
if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
cpu_has(c, X86_FEATURE_STIBP) ||
- cpu_has(c, X86_FEATURE_AMD_SPEC_CTRL) ||
- cpu_has(c, X86_FEATURE_AMD_PRED_CMD) ||
+ cpu_has(c, X86_FEATURE_AMD_IBRS) ||
+ cpu_has(c, X86_FEATURE_AMD_IBPB) ||
cpu_has(c, X86_FEATURE_AMD_STIBP)) && bad_spectre_microcode(c)) {
pr_warn("Intel Spectre v2 broken microcode detected; disabling
SPEC_CTRL\n");
clear_cpu_cap(c, X86_FEATURE_SPEC_CTRL);
clear_cpu_cap(c, X86_FEATURE_STIBP);
- clear_cpu_cap(c, X86_FEATURE_AMD_SPEC_CTRL);
- clear_cpu_cap(c, X86_FEATURE_AMD_PRED_CMD);
+ clear_cpu_cap(c, X86_FEATURE_AMD_IBRS);
+ clear_cpu_cap(c, X86_FEATURE_AMD_IBPB);
clear_cpu_cap(c, X86_FEATURE_AMD_STIBP);
}
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
