From: Roman Li <roman...@amd.com>
[ Upstream commit c6888879fd55b1ba903c2a770127edbf6aef6f27 ]
[Why]
More than 4x4K didn't lightup on Vega20 due to low dcfclk value.
Powerplay expects valid min requirement for dcfclk from DC.
[How]
Update min_dcfclock_khz based on min_engine_clock value.
v2: backport to 4.20 (Alex)
Reviewed-by: Hersen Wu <hersenxs...@amd.com>
Reviewed-by: Feifei Xu <feifei...@amd.com>
Reviewed-by: Evan Quan <evan.q...@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Roman Li <roman...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Sasha Levin <sas...@kernel.org>
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index b2f308766a9e..0941f3c689bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2530,6 +2530,8 @@ static void pplib_apply_display_requirements(
dc,
context->bw.dce.sclk_khz);
+ pp_display_cfg->min_dcfclock_khz = pp_display_cfg->min_engine_clock_khz;
+
pp_display_cfg->min_engine_clock_deep_sleep_khz
= context->bw.dce.sclk_deep_sleep_khz;
--
2.19.1
