Hello Andrew,

On Sun, 20 Jan 2019 19:51:07 +0100
Andrew Lunn <and...@lunn.ch> wrote:

>On Fri, Jan 18, 2019 at 04:23:46PM +0100, Maxime Chevallier wrote:
>> Marvell 10G PHY driver has a generic way of initializing the supported
>> link modes by reading the PHY's C45 PMA abilities. This can be made
>> generic, since these registers are part of the 802.3 specifications.
>> 
>> This commit extracts the config_init link_mode initialization code from
>> marvell10g and uses it to introduce the genphy_c45_read_abilities
>> function.  
>
>Hi Maxime
>
>I think the idea is good. I just have a few English language
>issues/questions.

Thanks for the review.

>Capabilities is more often used than abilities. I just wondered if
>abilities is taken from the 802.3 specifications?

Yes, the term 'Ability' is used in the 802.3 specifications, both in
the register names and the descriptions.

>Also, i wonder if we should include _pma_ in the name? At some point
>we might want to do something similar for other sublayers.

You're right, we do read only from the PMA and I see that we could also
to similar thing for the PCS layer, I'll rename the function.

>> +/**
>> + * genphy_c45_read_abilities - read supported link modes from PMA
>> + * @phydev: target phy_device struct
>> + *
>> + * Read the supported link modes from the PMA Status 2 (1.8) register. If 
>> bit
>> + * 1.8.9 is set, the list of supported modes is completed with the values 
>> in the  
>
>completed is not the right word. 'is build using the values in the' ?

That's better indeed, I'll correct that sentence.

>> + * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G 
>> related
>> + * modes. If bit 1.11.14 is set, then the list is also completed with the 
>> modes  
>
>list is also extended with the modes

And that one too.

>> + * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
>> + * 5GBASET are supported.
>> + */  
>

Thanks,

Maxime

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