On Fri, May 10, 2019 at 12:49:55PM -0700, Florian Fainelli wrote: > On 5/6/19 12:25 AM, John Garry wrote: > > On 03/05/2019 00:47, Florian Fainelli wrote: > >> The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events > >> up to the RC_ST_SPEC (0x91) event with the exception of: > >> > >> - L1D_CACHE_REFILL_INNER (0x44) > >> - L1D_CACHE_REFILL_OUTER (0x45) > >> - L1D_TLB_RD (0x4E) > >> - L1D_TLB_WR (0x4F) > >> - L2D_TLB_REFILL_RD (0x5C) > >> - L2D_TLB_REFILL_WR (0x5D) > >> - L2D_TLB_RD (0x5E) > >> - L2D_TLB_WR (0x5F) > >> - STREX_SPEC (0x6F) > >> > >> Create an appropriate JSON file for mapping those events and update the > >> mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that > >> file. > > > > I suppose you could have also created separate a72 and a57 folders, and > > used a symbolic link for the json. That would have kept the folder > > structure consistent and neat. > > Will, Mark, any preference on that? Either way works fine.
I'd personally avoid committing symbolic links if possible, so I'm fine with your patch as-is. Will
