On Thu, May 02, 2019 at 04:47:04PM -0700, Florian Fainelli wrote: > diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv > b/tools/perf/pmu-events/arch/arm64/mapfile.csv > index 59cd8604b0bd..69a73957e35c 100644 > --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv > +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv > @@ -13,6 +13,8 @@ > # > #Family-model,Version,Filename,EventType > 0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core > +0x00000000411fd07[[:xdigit:]],v1,arm/cortex-a57-a72,core
The 4-bit variant field should be 0x0, not 0x1. In fact, I think we could do the same for the revision field too and use 0x0 instead of [[:xdigit:]] for Cortex-A53, no? Our implementation of get_cpuid_str() masks these out for us. Am I missing something? Will
