Hi Martin,
Thanks for the review, we really appreciate your time.
Please see my comments below.
On 2019/9/6 4:15, Martin Blumenstingl wrote:
> Hi Jianxin,
>
> (it's great to see that you and your team are upstreaming this early)
>
> On Thu, Sep 5, 2019 at 9:08 AM Jianxin Pan <jianxin....@amlogic.com> wrote:
> [...]
>> + memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x8000000>;
>> + /*linux,usable-memory = <0x0 0x0 0x0 0x8000000>;*/
> why do we need that comment here (I don't understand it - why doesn't
> the "reg" property cover this)?
> I replaced "linux,usable-memory" with reg, but forgot to remove this comment
> line.
I will remove this line in the next version. Thank you.
>> + };
>> +};
>> +
>> +&uart_AO_B {
>> + status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> new file mode 100644
>> index 00000000..4d476ac
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> @@ -0,0 +1,122 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> + compatible = "amlogic,a1";
>> +
>> + interrupt-parent = <&gic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <0x2>;
>> + #size-cells = <0x0>;
> only now I notice that all our other .dtsi also use hex values
> (instead of decimal as just a few lines above) here
> do you know if there is a particular reason for this?
>
I just copied from the previous series, and didn't notice the difference
before.> [...]
>> + uart_AO_B: serial@fe002000 {
>> + compatible = "amlogic,meson-gx-uart",
>> + "amlogic,meson-ao-uart";
>> + reg = <0x0 0xfe002000 0x0 0x18>;
> the indentation of the "reg" property is off here
OK, I will fix it.
>
> also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...)
> here
> aren't there any busses defined in the A1 SoC implementation or are
> were you planning to add them later?
>Unlike previous series,there is no Cortex-M3 AO CPU in A1, and there is no
>AO/EE power domain.
Most of the registers are on the apb_32b bus. aobus, cbus and periphs are not
used in A1.
>
> Martin
>
> .
>
