[PATCH V2 3/3] clk: imx8mp: add mu root clk

[peng . fan]

From: Peng Fan <peng....@nxp.com>

Add mu root clk for mu mailbox usage.

Signed-off-by: Peng Fan <peng....@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.d...@nxp.com>
---
 drivers/clk/imx/clk-imx8mp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index b4d9db9d5bf1..ca747712400f 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -680,6 +680,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
        hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", 
ccm_base + 0x4180, 0);
        hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", 
ccm_base + 0x4190, 0);
        hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", 
ccm_base + 0x41a0, 0);
+       hws[IMX8MP_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", 
ccm_base + 0x4210, 0);
        hws[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", 
"ipg_root", ccm_base + 0x4220, 0);
        hws[IMX8MP_CLK_PCIE_ROOT] = imx_clk_hw_gate4("pcie_root_clk", 
"pcie_aux", ccm_base + 0x4250, 0);
        hws[IMX8MP_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", 
ccm_base + 0x4280, 0);
-- 
2.16.4