From: Peng Fan <peng....@nxp.com>

Add mu node to let A53 could communicate with M Core.

Signed-off-by: Peng Fan <peng....@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +++++++++
 arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +++++++++
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 9 +++++++++
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +++++++++
 4 files changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi 
b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index aaf6e71101a1..fc001fb971e9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -775,6 +775,15 @@
                                status = "disabled";
                        };
 
+                       mu: mailbox@30aa0000 {
+                               compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
+                               reg = <0x30aa0000 0x10000>;
+                               interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MM_CLK_MU_ROOT>;
+                               clock-names = "mu";
+                               #mbox-cells = <2>;
+                       };
+
                        usdhc1: mmc@30b40000 {
                                compatible = "fsl,imx8mm-usdhc", 
"fsl,imx7d-usdhc";
                                reg = <0x30b40000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi 
b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 9a4b65a267d4..c8290d21ccc9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -675,6 +675,15 @@
                                status = "disabled";
                        };
 
+                       mu: mailbox@30aa0000 {
+                               compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
+                               reg = <0x30aa0000 0x10000>;
+                               interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MN_CLK_MU_ROOT>;
+                               clock-names = "mu";
+                               #mbox-cells = <2>;
+                       };
+
                        usdhc1: mmc@30b40000 {
                                compatible = "fsl,imx8mn-usdhc", 
"fsl,imx7d-usdhc";
                                reg = <0x30b40000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi 
b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 45e2c0a4e889..b530804f763e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -621,6 +621,15 @@
                                status = "disabled";
                        };
 
+                       mu: mailbox@30aa0000 {
+                               compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
+                               reg = <0x30aa0000 0x10000>;
+                               interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MP_CLK_MU_ROOT>;
+                               clock-names = "mu";
+                               #mbox-cells = <2>;
+                       };
+
                        i2c5: i2c@30ad0000 {
                                compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
                                #address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi 
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 978f8122c0d2..66ba8da704f6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -959,6 +959,15 @@
                                status = "disabled";
                        };
 
+                       mu: mailbox@30aa0000 {
+                               compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
+                               reg = <0x30aa0000 0x10000>;
+                               interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
+                               clock-names = "mu";
+                               #mbox-cells = <2>;
+                       };
+
                        usdhc1: mmc@30b40000 {
                                compatible = "fsl,imx8mq-usdhc",
                                             "fsl,imx7d-usdhc";
-- 
2.16.4

Reply via email to