On Fri, 10 Jul 2020, at 05:27, Eddie James wrote: > When calculating the clock divider, start dividing at 2 instead of 1. > The divider is divided by two at the end of the calculation, so starting > at 1 may result in a divider of 0, which shouldn't happen. > > Signed-off-by: Eddie James <eaja...@linux.ibm.com> Reviewed-by: Andrew Jeffery <and...@aj.id.au>
- [PATCH 0/2] clk: Aspeed: Fix eMMC clock speeds Eddie James
- [PATCH 1/2] clk: AST2600: Add mux for EMMC clock Eddie James
- [PATCH 2/2] mmc: sdhci-of-aspeed: Fix clock divider ca... Eddie James
- Re: [PATCH 2/2] mmc: sdhci-of-aspeed: Fix clock di... Andrew Jeffery
- Re: [PATCH 2/2] mmc: sdhci-of-aspeed: Fix cloc... Joel Stanley
- Re: [PATCH 2/2] mmc: sdhci-of-aspeed: Fix clock di... Adrian Hunter
- Re: [PATCH 2/2] mmc: sdhci-of-aspeed: Fix clock di... Ulf Hansson
- Re: [PATCH 2/2] mmc: sdhci-of-aspeed: Fix cloc... Andrew Jeffery
- Re: [PATCH 2/2] mmc: sdhci-of-aspeed: Fix clock di... Ulf Hansson