On Thu, Oct 22, 2020 at 10:08:06AM -0500, Adam Ford wrote:
> This adds the DT nodes to describe the power domains available on the
> i.MX8MN. There are four power domains, but the displaymix and mipi
> power domains need a separate clock block controller which is also
> pending for 8MP and 8MM. Once the path for those is clear, Nano will
> need something similar, but the registers for Nano differ. For now,
> the dispmix and mipi are placeholders.
>
> Signed-off-by: Adam Ford <[email protected]>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 9b4baf7bdfb1..27733fbe87e9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -596,6 +596,55 @@ src: reset-controller@30390000 {
> interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> #reset-cells = <1>;
> };
> +
> + gpc: gpc@303a0000 {
> + compatible = "fsl,imx8mn-gpc";
> + reg = <0x303a0000 0x10000>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
Missing interrupts.
> +
> + pgc {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pgc_hsiomix: power-domain@0 {
> + #power-domain-cells = <0>;
> + reg =
> <IMX8MN_POWER_DOMAIN_HSIOMIX>;
> + clocks = <&clk
> IMX8MN_CLK_USB_BUS>;
> + };
> +
> + pgc_otg1: power-domain@1 {
> + #power-domain-cells = <0>;
> + reg =
> <IMX8MN_POWER_DOMAIN_OTG1>;
> + power-domains = <&pgc_hsiomix>;
> + };
> +
> + pgc_gpumix: power-domain@2 {
> + #power-domain-cells = <0>;
> + reg =
> <IMX8MN_POWER_DOMAIN_GPUMIX>;
> + clocks = <&clk
> IMX8MN_CLK_GPU_CORE_ROOT>,
> + <&clk
> IMX8MN_CLK_GPU_SHADER_DIV>,
> + <&clk
> IMX8MN_CLK_GPU_BUS_ROOT>,
> + <&clk
> IMX8MN_CLK_GPU_AHB>;
> + resets = <&src
> IMX8MQ_RESET_GPU_RESET>;
Does it compile without include? Did the include come via dependencies
of this patch?
Best regards,
Krzysztof
