On 11/9/20 11:35 AM, Arvind Sankar wrote: > The PAT bit is in different locations for 4k and 2M/1G page table > entries. > > Add a definition for _PAGE_LARGE_CACHE_MASK to represent the three > caching bits (PWT, PCD, PAT), similar to _PAGE_CACHE_MASK for 4k pages, > and use it in the definition of PMD_FLAGS_DEC_WP to get the correct PAT > index for write-protected pages. > > Remove a duplication definition of _PAGE_PAT_LARGE. > > Signed-off-by: Arvind Sankar <nived...@alum.mit.edu>
Fixes: tag? Tested-by: Tom Lendacky <thomas.lenda...@amd.com> > --- > arch/x86/include/asm/pgtable_types.h | 3 +-- > arch/x86/mm/mem_encrypt_identity.c | 4 ++-- > 2 files changed, 3 insertions(+), 4 deletions(-) >
