В сообщении от Wednesday 26 December 2007 12:17:56 Arjan van de Ven написал(а): > On Wed, 26 Dec 2007 00:09:57 +0100 > Pavel Machek <[EMAIL PROTECTED]> wrote: > > > On Sat 2007-12-22 12:09:59, Arjan van de Ven wrote: > > > On Tue, 18 Dec 2007 17:06:24 +0000 > > > > memtest86+ does various magic to basically bypass the caches (by > > > disabling them ;-)... Doing that in a live kernel situation, and > > > from userspace to boot...... that's... and issue. > > > > Are you sure? I always assumed that memtest just used patterns bigger > > than L1/L2 caches... > > that's... not nearly usable or enough. Caches are relatively smart > about things like use-once.... and they're huge. 12Mb today. You'd need > patterns bigger than 100Mb to get even close to being reasonably > confident that there's nothing left. > > > ... and IIRC my celeron testing confirmed it, if > > I disabled L2 cache in BIOS, memtest behave differently. > > > > Anyway, if you can do iopl(), we may as well let you disable caches, > > but you are right, that will need a kernel patch. > > and a new syscall of some sorts I suspect; "flush all caches" is a ring > 0 operation (and you probably need to do it in an ipi anyway on all > cpus) >
I think that PAT support will help a lot. How about opening/mmaping /dev/mem, and setting uncacheable attribute there. Actually it is even possible today with MTRRs. Regards, Maxim Levitsky -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/