Hello Peter,
On 27/01/2021 23:32, Peter Zijlstra wrote:
>> Link: https://lore.kernel.org/lkml/5644d08d.4080...@caviumnetworks.com/
please, check the discussion pointed by the link above...
>> Signed-off-by: Alexander Sverdlin <alexander.sverd...@nokia.com>
>> ---
>> arch/mips/include/asm/barrier.h | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/mips/include/asm/barrier.h
>> b/arch/mips/include/asm/barrier.h
>> index 49ff172..24c3f2c 100644
>> --- a/arch/mips/include/asm/barrier.h
>> +++ b/arch/mips/include/asm/barrier.h
>> @@ -113,6 +113,15 @@ static inline void wmb(void)
>> ".set arch=octeon\n\t" \
>> "syncw\n\t" \
>> ".set pop" : : : "memory")
>> +
>> +#define __smp_store_release(p, v) \
>> +do {
>> \
>> + compiletime_assert_atomic_type(*p); \
>> + __smp_wmb(); \
>> + __smp_rmb(); \
>> + WRITE_ONCE(*p, v); \
>> +} while (0)
> This is wrong in general since smp_rmb() will only provide order between
> two loads and smp_store_release() is a store.
>
> If this is correct for all MIPS, this needs a giant comment on exactly
> how that smp_rmb() makes sense here.
... the macro is provided for Octeon only, and __smp_rmb() is actually a NOP
there, but I thought to "document" the flow of thoughts from the discussion
above by including it anyway.
--
Best regards,
Alexander Sverdlin.
