Break up long values to pass dt-schema checks.
Signed-off-by: Li Yang <leoyang...@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 4bf6320c85d9..959a3c85b83e 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -842,8 +842,8 @@
pcie@3400000 {
compatible = "fsl,ls1021a-pcie";
- reg = <0x00 0x03400000 0x0 0x00010000 /* controller
registers */
- 0x40 0x00000000 0x0 0x00002000>; /*
configuration space */
+ reg = <0x00 0x03400000 0x0 0x00010000>, /* controller
registers */
+ <0x40 0x00000000 0x0 0x00002000>; /*
configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /*
controller interrupt */
fsl,pcie-scfg = <&scfg 0>;
@@ -852,8 +852,8 @@
device_type = "pci";
num-viewport = <6>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0
0x00010000 /* downstream I/O */
- 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0
0x00010000>, /* downstream I/O */
+ <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
msi-parent = <&msi1>, <&msi2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
@@ -866,8 +866,8 @@
pcie@3500000 {
compatible = "fsl,ls1021a-pcie";
- reg = <0x00 0x03500000 0x0 0x00010000 /* controller
registers */
- 0x48 0x00000000 0x0 0x00002000>; /*
configuration space */
+ reg = <0x00 0x03500000 0x0 0x00010000>, /* controller
registers */
+ <0x48 0x00000000 0x0 0x00002000>; /*
configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
fsl,pcie-scfg = <&scfg 1>;
@@ -876,8 +876,8 @@
device_type = "pci";
num-viewport = <6>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0
0x00010000 /* downstream I/O */
- 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0
0x00010000>, /* downstream I/O */
+ <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
msi-parent = <&msi1>, <&msi2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
--
2.17.1
