The OV10640 image sensor reset and powerdown on signals are controlled
by the embedded OV490 ISP. The current reset procedure does not respect
the 1 millisecond power-up delay and releases the reset signal before
the powerdown one.
Fix the OV10640 power up sequence by releasing the powerdown signal,
waiting the mandatory 1 millisecond power up delay and then releasing
the reset signal. The reset delay is not characterized in the chip
manual if not as "255 XVCLK + initialization". Wait for at least 3
milliseconds to guarantee the SCCB bus is available.
This commit fixes a sporadic start-up error triggered by a failure to
read the OV10640 chip ID:
rdacm21 8-0054: OV10640 ID mismatch: (0x01)
Signed-off-by: Jacopo Mondi <jacopo+rene...@jmondi.org>
---
drivers/media/i2c/rdacm21.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/rdacm21.c b/drivers/media/i2c/rdacm21.c
index b22a2ca5340b..c420a6b96879 100644
--- a/drivers/media/i2c/rdacm21.c
+++ b/drivers/media/i2c/rdacm21.c
@@ -333,13 +333,15 @@ static int ov10640_initialize(struct rdacm21_device *dev)
{
u8 val;
- /* Power-up OV10640 by setting RESETB and PWDNB pins high. */
+ /* Power-up OV10640 by setting PWDNB and RESETB pins high. */
ov490_write_reg(dev, OV490_GPIO_SEL0, OV490_GPIO0);
ov490_write_reg(dev, OV490_GPIO_SEL1, OV490_SPWDN0);
ov490_write_reg(dev, OV490_GPIO_DIRECTION0, OV490_GPIO0);
ov490_write_reg(dev, OV490_GPIO_DIRECTION1, OV490_SPWDN0);
- ov490_write_reg(dev, OV490_GPIO_OUTPUT_VALUE0, OV490_GPIO0);
+
ov490_write_reg(dev, OV490_GPIO_OUTPUT_VALUE0, OV490_SPWDN0);
+ usleep_range(1500, 3000);
+ ov490_write_reg(dev, OV490_GPIO_OUTPUT_VALUE0, OV490_GPIO0);
usleep_range(3000, 5000);
/* Read OV10640 ID to test communications. */
--
2.30.0
