On Wed, Mar 03, 2021 at 02:53:00PM -0500, Liang, Kan wrote: > On 3/3/2021 1:59 PM, Peter Zijlstra wrote: > > On Wed, Mar 03, 2021 at 05:42:18AM -0800, kan.li...@linux.intel.com wrote:
> > > +++ b/arch/x86/events/intel/ds.c > > > @@ -2000,18 +2000,6 @@ static void intel_pmu_drain_pebs_nhm(struct > > > pt_regs *iregs, struct perf_sample_d > > > continue; > > > } > > > - /* > > > - * On some CPUs the PEBS status can be zero when PEBS is > > > - * racing with clearing of GLOBAL_STATUS. > > > - * > > > - * Normally we would drop that record, but in the > > > - * case when there is only a single active PEBS event > > > - * we can assume it's for that event. > > > - */ > > > - if (!pebs_status && cpuc->pebs_enabled && > > > - !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) > > > - pebs_status = cpuc->pebs_enabled; > > > > Wouldn't something like: > > > > pebs_status = p->status = cpus->pebs_enabled; > > > > I didn't consider it as a potential solution in this patch because I don't > think it's a proper way that SW modifies the buffer, which is supposed to be > manipulated by the HW. Right, but then HW was supposed to write sane values and it doesn't do that either ;-) > It's just a personal preference. I don't see any issue here. We may try it. So I mostly agree with you, but I think it's a shame to unsupport such chips, HSW is still a plenty useable chip today.
