This GDSC requires an interconnect path to be enabled, otherwise the GDSC will be stuck on 'off' and can't be enabled.
Signed-off-by: Luca Weiss <[email protected]> --- drivers/clk/qcom/camcc-milos.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/camcc-milos.c b/drivers/clk/qcom/camcc-milos.c index 0077c9c9249f..45e68165a2f0 100644 --- a/drivers/clk/qcom/camcc-milos.c +++ b/drivers/clk/qcom/camcc-milos.c @@ -30,6 +30,11 @@ enum { DT_IFACE, }; +/* Need to match the order of interconnects in DT binding */ +enum { + DT_ICC_TOP_GDSC, +}; + enum { P_BI_TCXO, P_CAM_CC_PLL0_OUT_EVEN, @@ -1971,6 +1976,8 @@ static struct gdsc cam_cc_camss_top_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .needs_icc = true, + .icc_path_index = DT_ICC_TOP_GDSC, }; static struct clk_regmap *cam_cc_milos_clocks[] = { -- 2.52.0
