On Fri, Jan 16, 2026 at 02:17:21PM +0100, Luca Weiss wrote: > Document an interconnect path for camcc that's required to enable > the CAMSS_TOP_GDSC power domain.
I find it confusing. Enabling GDSC power domains is done via power domains, not via interconnects. Do not represent power domains as interconnects, it's something completely different. > > Signed-off-by: Luca Weiss <[email protected]> > --- > Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml > b/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml > index f63149ecf3e1..707b25d2c11e 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml > @@ -25,6 +25,10 @@ properties: > - description: Sleep clock source > - description: Camera AHB clock from GCC > > + interconnects: > + items: > + - description: Interconnect path to enable the MultiMedia NoC And since when clock controllers are part of interconnect path... Even more questions.... Best regards, Krzysztof
