> > AFAIK mapping PCI memory WB is not allowed, so WC is really our only > > choice.
> afaik that depends on the BAR being prefetchable or not. In my case the BAR is prefetchable. > (and by your argument, ioremap_cached() would not be useful, and since that > was, until > 2.6.25-rc1, the default behavior for ioremap(), would have caused massive > problems) I'm not sure what ioremap_cached() would really do in my case, since the MTRRs for PCI memory are set to UC, so without monkeying with MTRR contents (which can't really be done safely) the only choices we have are leaving the mapping as UC or using PAT to get WC. Also in my case I'm more concerned about latency of finishing a small write rather than througput. So I'm not sure that I would really want to do a write to a WB mapping followed by CLFLUSH anyway. - R. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
