On Fri, 2013-01-25 at 10:47 +0100, Linus Walleij wrote:
> On Thu, Jan 24, 2013 at 9:52 PM, Aaron Sierra <asie...@xes-inc.com> wrote:
>
> > In ICH5 and earlier the GPIOBASE and GPIOCTRL registers are found at
> > offsets 0x58 and 0x5C, respectively. This patch allows GPIO access to
> > properly be enabled (and disabled) for these chipsets.
> >
> > Signed-off-by: Agócs Pál <agocs.pal...@gmail.com>
> > Signed-off-by: Aaron Sierra <asie...@xes-inc.com>
>
> OK... Paul, can you test this on your setup?
>
> > @@ -858,14 +874,35 @@ wdt_done:
> > static int lpc_ich_probe(struct pci_dev *dev,
> > const struct pci_device_id *id)
> > {
> > + struct lpc_ich_priv *priv;
> > int ret;
> > bool cell_added = false;
> >
> > - ret = lpc_ich_init_wdt(dev, id);
> > + priv = kmalloc(GFP_KERNEL, sizeof(struct lpc_ich_priv));
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->chipset = id->driver_data;
>
> So where is this id->driver_data which is just assigned to
> priv->chipset coming from again? ACPI something?
That's how pci device probing works.
The driver defines a struct pci_device_id[] table with
DEFINE_PCI_DEVICE_TABLE(), initializing the .driver_data fields with an
index into a static array of device types (in this case, struct
lpc_ich_info lpc_chipset_info[]), and the pci subsystem passes the
actual matching pci_device_id* to the driver's probe() function.
There's more information in Documentation/pci.txt
Regards,
Peter Hurley
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