Hi Linus, On Fri, Jan 25, 2013 at 10:47:45AM +0100, Linus Walleij wrote: > On Thu, Jan 24, 2013 at 9:52 PM, Aaron Sierra <[email protected]> wrote: > > > In ICH5 and earlier the GPIOBASE and GPIOCTRL registers are found at > > offsets 0x58 and 0x5C, respectively. This patch allows GPIO access to > > properly be enabled (and disabled) for these chipsets. > > > > Signed-off-by: Agócs Pál <[email protected]> > > Signed-off-by: Aaron Sierra <[email protected]> > > OK... Paul, can you test this on your setup? > > > @@ -858,14 +874,35 @@ wdt_done: > > static int lpc_ich_probe(struct pci_dev *dev, > > const struct pci_device_id *id) > > { > > + struct lpc_ich_priv *priv; > > int ret; > > bool cell_added = false; > > > > - ret = lpc_ich_init_wdt(dev, id); > > + priv = kmalloc(GFP_KERNEL, sizeof(struct lpc_ich_priv)); > > + if (!priv) > > + return -ENOMEM; > > + > > + priv->chipset = id->driver_data; > > So where is this id->driver_data which is just assigned to > priv->chipset coming from again? ACPI something? It comes from the static PCI table the driver defines itself. It allows you to pass meta data associated to a specific PCI ID.
Cheers, Samuel. -- Intel Open Source Technology Centre http://oss.intel.com/ -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
