On 04/29/2014 07:06 AM, Steven Rostedt wrote:
> On Tue, 29 Apr 2014 06:29:04 -0700
> "H. Peter Anvin" <h...@linux.intel.com> wrote:
>
>
>>> [2] "A special case can occur if an SMI handler nests inside an NMI
>>> handler and then another NMI occurs. During NMI interrupt
>>> handling, NMI interrupts are disabled, so normally NMI interrupts
>>> are serviced and completed with an IRET instruction one at a
>>> time. When the processor enters SMM while executing an NMI
>>> handler, the processor saves the SMRAM state save map but does
>>> not save the attribute to keep NMI interrupts disabled.
>>> Potentially, an NMI could be latched (while in SMM or upon exit)
>>> and serviced upon exit of SMM even though the previous NMI
>>> handler has still not completed."
>>
>> I believe [2] only applies if there is an IRET executing inside the SMM
>> handler, which should not normally be the case. It might also have been
>> addressed since that was written, but I don't know.
>
> Bad behaving BIOS? But I'm sure there's no such thing ;-)
>
Never...
-hpa
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