On 11/05/2014 09:09 PM, bpqw wrote: > This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. > > For Micron SPI NOR flash,enabling or disabling quad I/O protocol is > controlled > by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7. > When EVCR bit 7 is reset to 0,the SPI NOR flash will operate in quad I/O > mode.
Hi, I'm having trouble with this patch using a Cadence QSPI controller and Micron n25q00 part. I can use quad commands in Extended SPI mode, but I can't make this EVCR Quad mode work. The Cadence QSPI Controller has fields to configure the quad transfer, and can support quad opcode, quad address, and quad data, or some combination. There is a chart in the docs which shows the combinations for various read commands. Problem is, I've tried all of the combinations and all I get is FF with this EVCR patch. If I don't set the quad mode in the EVCR, then I can use quad read commands no problem. Bottom line, with the Cadence QSPI controller, if I use quad commands in Extended SPI mode, then all good. If I use this EVCR quad mode, then all bad. Anybody else have a Cadence QSPI controller and using EVCR quad mode successfully? Thanks, Graham Moore -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
