On Sun, 27 Dec 1998, Denoid Tucker wrote:
> Intel is marketing the Celeron for the "low-end" PC. They designed the chip
> NOT to work in SMP configurations. When the chips senses that it is part of a
> SMP config, it fails to boot. This is part of the design even though the
> chips are basically regular PII's w/o the L2 cache. You can, however, "fool"
> the chip into thinking that it is in a single config but it is a non trivial
> task. I do very much recommend Mr. Cinege's suggestion of over-clocking
> regular PII 300 or 333's. Check out
> http://www.tomshardware.com/Celeronto100.html .
This is not correct on two accounts. There _is_ an L2 cache, it is
integrated on the die and also running at full speed just like the xeon L2
cache and not at half speed like the ordinary PIIs. Benchmarks posted a
while ago on linux-kernel showed that the celeron 300A was outperforming
regular PIIs for tasks exhibiting good code and data locallity.
The second error is regarding SMP operations. The celeron _chip_ is fully
smp capable, I suspect Intel used the same cpu core on the chip as in
their other PIIs. The problem is with the board the chip is mounted on.
It is far cheaper to redesign a printed circuit board than a chip, I
suspect they wanted the option to manefacture a smp-capable celeron later.
Anyway, the problem is that one signal used in smp configurations is not
connected from the slot-1 connector to the chip. Instead the signal is
connected to +2V. By removing the phony connection to +2V and wire the
signal correctly to the slot-1 connector you get a smp capable celeron.
See http://kikumaru.w-w.ne.jp/pc/celeron/index_e.html for a description of
how to do it.
Peter
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