Mark Garlanger writes:
> Richard Gooch wrote:
> >
> > Dave Cinege writes:
> > > Richard Gooch wrote:
> > > >
> > > > Bryan Burlingame writes:
> > > > > The new Celerons (300A and 333) have 128K of L2 cache clocked at the
> > > > > processor speed (ala Xeon) compared to the PII's that have 512K of L2 cache
> > > > > clocked at 1/2 the processor speed.
> > > >
> > > > But that doesn't answer my question. Dave was comparing a Celeron 300A
> > > > with a PII with "full speed cache". AFAIK a PII with full speed cache
> > > > is a Xeon. I'm not aware of a non-Xeon PII with full speed cache. I
> > > > wanted to make sure I knew exactly what Dave meant.
> > >
> > > What I meant is the newer PII's (>=333MHz) run their cache at full speed.
> > >
> > > Looking over some things I think I'm mistakin though, and was confusing this
> > > with the extended memory caching of the 'server' model PII's..
> >
> > OK, that clears it up. IIRC the older PIIs had L2 at bus speed (either
> > 66 MHz or 100 MHz depending on your system). The newer PIIs have L2 at
> > half CPU core speed. A definate improvement considering the higher and
> > higher core speeds we're seeing (450 MHz last time I looked).
> >
>
> Wrong....
> Currently:
> All regular PIIs (not celeron or xeon) at ANY speed runs it's cache
> at 1/2 the processor speed, and have 512K of cache.
> Celerons at 266 and 300(non-a) have 0(zero) cache.
> Celerons at 300a and 333 have 128K of cache at full processor speed.
> Xeons have 512k, 1M, or 2M of Level 2 cache running at full processor
> speed.
Ah, yeah. Sorry, you're right. I was confusing it with the change from
66 MHz FSB to 100 MHZ FSB.
Regards,
Richard....
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