Peter Svensson wrote:
> This is not correct on two accounts. There _is_ an L2 cache, it is
> integrated on the die and also running at full speed just like the xeon L2
> cache and not at half speed like the ordinary PIIs. Benchmarks posted a
> while ago on linux-kernel showed that the celeron 300A was outperforming
> regular PIIs for tasks exhibiting good code and data locallity.
FYI I've been performing some benchmarks behind the seens with some people that
have real PII's.
In a SMP benchs that makes *heavy* use of the cache, Dual 300'A @463MHz w/128K
L2 perform nearly identical to PII 400's w/512K L2 FULL SPEED cache.
For normal operations the Celerons beat up the PII's.
I would like to see some benchs against half speed cache PII's. I would guess
they are no faster then the Celerons.
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