From: Bill Huang <bilhu...@nvidia.com>
This fixes bug in tegra_clk_register_pllss() which mistakenly assume the
iddq register is the PLL base address.
Signed-off-by: Bill Huang <bilhu...@nvidia.com>
Reviewed-by: Benson Leung <ble...@chromium.org>
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 932a18ce821f..82f04a60649c 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1921,7 +1921,7 @@ struct clk *tegra_clk_register_pllss(const char *name,
const char *parent_name,
struct clk *clk, *parent;
struct tegra_clk_pll_freq_table cfg;
unsigned long parent_rate;
- u32 val;
+ u32 val, val_iddq;
int i;
if (!pll_params->div_nmp)
@@ -1968,14 +1968,17 @@ struct clk *tegra_clk_register_pllss(const char *name,
const char *parent_name,
pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
val = pll_readl_base(pll);
+ val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
if (val & PLL_BASE_ENABLE) {
- if (val & BIT(pll_params->iddq_bit_idx)) {
+ if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
WARN(1, "%s is on but IDDQ set\n", name);
kfree(pll);
return ERR_PTR(-EINVAL);
}
- } else
- val |= BIT(pll_params->iddq_bit_idx);
+ } else {
+ val_iddq |= BIT(pll_params->iddq_bit_idx);
+ writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
+ }
val &= ~PLLSS_LOCK_OVERRIDE;
pll_writel_base(val, pll);
--
1.7.9.5
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