This reverts commit e9e44fc88abadc52ca6b0f1f8307e6967ddbec22.

The clock driver clk-imx8qxp-lpcg still uses LPCG bit-offset instead of
clock-indices for clock-controller dts properties, so it can not switch
to use lpcg indices.

Signed-off-by: Xulin Sun <xulin....@windriver.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi 
b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index 8475b7a37316..0677cbef8f2b 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -32,8 +32,8 @@ lsio_pwm0: pwm@5d000000 {
                compatible = "fsl,imx27-pwm";
                reg = <0x5d000000 0x10000>;
                clock-names = "ipg", "per";
-               clocks = <&pwm0_lpcg IMX_LPCG_CLK_6>,
-                        <&pwm0_lpcg IMX_LPCG_CLK_1>;
+               clocks = <&pwm0_lpcg 4>,
+                        <&pwm0_lpcg 1>;
                assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
                #pwm-cells = <3>;
@@ -45,8 +45,8 @@ lsio_pwm1: pwm@5d010000 {
                compatible = "fsl,imx27-pwm";
                reg = <0x5d010000 0x10000>;
                clock-names = "ipg", "per";
-               clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>,
-                        <&pwm1_lpcg IMX_LPCG_CLK_1>;
+               clocks = <&pwm1_lpcg 4>,
+                        <&pwm1_lpcg 1>;
                assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
                #pwm-cells = <3>;
@@ -58,8 +58,8 @@ lsio_pwm2: pwm@5d020000 {
                compatible = "fsl,imx27-pwm";
                reg = <0x5d020000 0x10000>;
                clock-names = "ipg", "per";
-               clocks = <&pwm2_lpcg IMX_LPCG_CLK_6>,
-                        <&pwm2_lpcg IMX_LPCG_CLK_1>;
+               clocks = <&pwm2_lpcg 4>,
+                        <&pwm2_lpcg 1>;
                assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
                #pwm-cells = <3>;
@@ -71,8 +71,8 @@ lsio_pwm3: pwm@5d030000 {
                compatible = "fsl,imx27-pwm";
                reg = <0x5d030000 0x10000>;
                clock-names = "ipg", "per";
-               clocks = <&pwm3_lpcg IMX_LPCG_CLK_6>,
-                        <&pwm3_lpcg IMX_LPCG_CLK_1>;
+               clocks = <&pwm3_lpcg 4>,
+                        <&pwm3_lpcg 1>;
                assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
                #pwm-cells = <3>;
-- 
2.34.1

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