Ollie Lho and I have worked together and we have tracked down what in
the K7 initialization is needed to get good resonable memory
performance. And it is not L2 cache initialization.
Since the information we were using comes from documents
we received under NDA we can't release anything, just yet.
All I can say is that the Alpha 21264 divides the memory space into two
major parts. One for memory and one for memory mapped io devices.
And it uses different kinds of bus cycles to the northbridge for
each part of it's memory space. The K7 effectively uses the same processor
bus, and does similiar things with memory. Just in a package that looks
like a classic x86 cpu. And the problem is related to what kind of cpu
bus cycle you generate.
Now if we can convince AMD to release documentation for their model specific
registers.
Eric
