Ollie Lho <[EMAIL PROTECTED]> writes:
> "Eric W. Biederman" wrote:
> >
> > Ollie Lho and I have worked together and we have tracked down what in
> > the K7 initialization is needed to get good resonable memory
> > performance. And it is not L2 cache initialization.
> >
> > Since the information we were using comes from documents
> > we received under NDA we can't release anything, just yet.
> >
> > All I can say is that the Alpha 21264 divides the memory space into two
> > major parts. One for memory and one for memory mapped io devices.
> > And it uses different kinds of bus cycles to the northbridge for
> > each part of it's memory space. The K7 effectively uses the same processor
> > bus, and does similiar things with memory. Just in a package that looks
> > like a classic x86 cpu. And the problem is related to what kind of cpu
> > bus cycle you generate.
> >
>
> Eric,
> Is there any public documents on the EV6 or S2K bus ?? I am really
> interrested in it. (Although I almost figured out everything I have to
> know
> doing SiS 730 stuff).
AMD has all of the documentation for the AMD762 northbridge publicly
available on their website. The EV6 information is a little tricky,
but buried around on Compaq site is fairly complete information for the 21264/EV6,
and it's supporting chipset the 21172. I have only seen S2K mentioned publicly
but I haven't seen anything go into any detail.
Eric
