Ollie Lho <[EMAIL PROTECTED]> writes:
> "Eric W. Biederman" wrote:
> >
> > Ollie Lho and I have worked together and we have tracked down what in
> > the K7 initialization is needed to get good resonable memory
> > performance. And it is not L2 cache initialization.
> >
>
> This seems to be "implied" by the AMD Porcessor Recognition App Note.
> It says only K7 CPUs of Model 1 and 2 need to init L2 cache.
> Model 1,2 are slot Athlon. Socket Atholon is Model 4 and Duron is
> Model 3.
>
> This has been explained by Bari in a private mail. (but I was too
> stupid to know what he was talking about at that time).
As an quick test your you have more than L2 cache poblems if you can
feel the slowdown. With L1 working on a light workload you will
not notice the absence of L2 cache.
This was true on the slot PII's where the problem was L2 cache
initialization, and it is true again on the K7 where we didn't have an
L2 cache problem :)
Eric
