-----Original Message-----
From: arndbergm...@gmail.com <arndbergm...@gmail.com> On Behalf Of Arnd Bergmann
Sent: 2018年10月26日 15:01
To: Xiaowei Bao <xiaowei....@nxp.com>
Cc: Rob Herring <r...@kernel.org>; bhelg...@google.com; mark.rutl...@arm.com;
shawn...@kernel.org; Leo Li <leoyang...@nxp.com>; kis...@ti.com;
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<minghuan.l...@nxp.com>; Mingkai Hu <mingkai...@nxp.com>; Roy Zang
<roy.z...@nxp.com>; kstew...@linuxfoundation.org;
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Subject: Re: [PATCH 3/6] PCI: layerscape: Add the EP mode support
On 10/26/18, Xiaowei Bao <xiaowei....@nxp.com> wrote:
> From: Rob Herring <r...@kernel.org>
>> On Thu, Oct 25, 2018 at 07:08:58PM +0800, Xiaowei Bao wrote:
>>> "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
>>> "fsl,ls2088a-pcie"
>>> "fsl,ls1088a-pcie"
>>> "fsl,ls1046a-pcie"
>>> "fsl,ls1012a-pcie
>>> + EP mode:
>>> + "fsl,ls-pcie-ep"
>>
> > You need SoC specific compatibles for the same reasons as the RC.
>
> [Xiaowei Bao] I want to contains all layerscape platform use one
> compatible if the PCIe controller work in EP mode.
Do you mean only one of the SoCs that support RC mode has EP mode?
I think you still need a SoC specific compatible as Rob explained, in case
there will be a second one in the future.
If you want to ensure that you don't have to update the device driver for each
new chip that comes in when the EP mode is compatible, the way this is handled
is to list multiple values in the compatible property, listing the first SoC
that introduced the specific version of that IP block as the most generic type,
e.g.
copatible = "fsl,ls2088a-pcie-ep", "fsl,ls1012a-pcie-ep", "snps,dw-pcie-ep";
For consistency, it probably is best to match each RC mode value with the
corresponding EP mode string for each device that can support both (if there is
more than one).
Arnd
[Xiaowei Bao] My mean is that the ls-pcie-ep compatibles will contain all
layerscape SOCs of NXP, e.g: ls1046a-pcie-ep, fsl,ls2088a-pcie-ep,
ls2088a-pcie-ep and so on, other layerscape SOCs have not test except the
ls1046a, I think it is compatible if the new chip or other SOCs use the DW
core, OK, I will discuss this issue internally, and reply to you later.
