From: Madhavan Srinivasan <ma...@linux.vnet.ibm.com> Create powerpc specific definitions for pipeline hazard and stalls. This information is available in SIER register on powerpc. Current definitions are based on IBM PowerPC SIER specification available in ISA[1] and Performance Monitor Unit User’s Guide[2].
[1]: Book III, Section 9.4.10: https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0 [2]: https://wiki.raptorcs.com/w/images/6/6b/POWER9_PMU_UG_v12_28NOV2018_pub.pdf#G9.1106986 Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com> Signed-off-by: Ravi Bangoria <ravi.bango...@linux.ibm.com> --- .../include/uapi/asm/perf_pipeline_haz.h | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 arch/powerpc/include/uapi/asm/perf_pipeline_haz.h diff --git a/arch/powerpc/include/uapi/asm/perf_pipeline_haz.h b/arch/powerpc/include/uapi/asm/perf_pipeline_haz.h new file mode 100644 index 000000000000..de8857ec31dd --- /dev/null +++ b/arch/powerpc/include/uapi/asm/perf_pipeline_haz.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _UAPI_ASM_POWERPC_PERF_PIPELINE_HAZ_H +#define _UAPI_ASM_POWERPC_PERF_PIPELINE_HAZ_H + +enum perf_inst_type { + PERF_HAZ__ITYPE_LOAD = 1, + PERF_HAZ__ITYPE_STORE, + PERF_HAZ__ITYPE_BRANCH, + PERF_HAZ__ITYPE_FP, + PERF_HAZ__ITYPE_FX, + PERF_HAZ__ITYPE_CR_OR_SC, +}; + +enum perf_inst_cache { + PERF_HAZ__ICACHE_L1_HIT = 1, + PERF_HAZ__ICACHE_L2_HIT, + PERF_HAZ__ICACHE_L3_HIT, + PERF_HAZ__ICACHE_L3_MISS, +}; + +enum perf_pipeline_stage { + PERF_HAZ__PIPE_STAGE_IFU = 1, + PERF_HAZ__PIPE_STAGE_IDU, + PERF_HAZ__PIPE_STAGE_ISU, + PERF_HAZ__PIPE_STAGE_LSU, + PERF_HAZ__PIPE_STAGE_BRU, + PERF_HAZ__PIPE_STAGE_FXU, + PERF_HAZ__PIPE_STAGE_FPU, + PERF_HAZ__PIPE_STAGE_VSU, + PERF_HAZ__PIPE_STAGE_OTHER, +}; + +enum perf_haz_bru_reason { + PERF_HAZ__HAZ_BRU_MPRED_DIR = 1, + PERF_HAZ__HAZ_BRU_MPRED_TA, +}; + +enum perf_haz_isu_reason { + PERF_HAZ__HAZ_ISU_SRC = 1, + PERF_HAZ__HAZ_ISU_COL = 1, +}; + +enum perf_haz_lsu_reason { + PERF_HAZ__HAZ_LSU_ERAT_MISS = 1, + PERF_HAZ__HAZ_LSU_LMQ, + PERF_HAZ__HAZ_LSU_LHS, + PERF_HAZ__HAZ_LSU_MPRED, + PERF_HAZ__HAZ_DERAT_MISS, + PERF_HAZ__HAZ_LSU_LMQ_DERAT_MISS, + PERF_HAZ__HAZ_LSU_LHS_DERAT_MISS, + PERF_HAZ__HAZ_LSU_MPRED_DERAT_MISS, +}; + +enum perf_stall_lsu_reason { + PERF_HAZ__STALL_LSU_DCACHE_MISS = 1, + PERF_HAZ__STALL_LSU_LD_FIN, + PERF_HAZ__STALL_LSU_ST_FWD, + PERF_HAZ__STALL_LSU_ST, +}; + +enum perf_stall_fxu_reason { + PERF_HAZ__STALL_FXU_MC = 1, + PERF_HAZ__STALL_FXU_FC, +}; + +enum perf_stall_bru_reason { + PERF_HAZ__STALL_BRU_FIN_MPRED = 1, + PERF_HAZ__STALL_BRU_FC, +}; + +enum perf_stall_vsu_reason { + PERF_HAZ__STALL_VSU_MC = 1, + PERF_HAZ__STALL_VSU_FC, +}; + +enum perf_stall_other_reason { + PERF_HAZ__STALL_NTC, +}; + +#endif /* _UAPI_ASM_POWERPC_PERF_PIPELINE_HAZ_H */ -- 2.21.1