On Mon, Mar 02, 2020 at 10:53:44AM +0530, Ravi Bangoria wrote: > Modern processors export such hazard data in Performance > Monitoring Unit (PMU) registers. Ex, 'Sampled Instruction Event > Register' on IBM PowerPC[1][2] and 'Instruction-Based Sampling' on > AMD[3] provides similar information. > > Implementation detail: > > A new sample_type called PERF_SAMPLE_PIPELINE_HAZ is introduced. > If it's set, kernel converts arch specific hazard information > into generic format: > > struct perf_pipeline_haz_data { > /* Instruction/Opcode type: Load, Store, Branch .... */ > __u8 itype; > /* Instruction Cache source */ > __u8 icache; > /* Instruction suffered hazard in pipeline stage */ > __u8 hazard_stage; > /* Hazard reason */ > __u8 hazard_reason; > /* Instruction suffered stall in pipeline stage */ > __u8 stall_stage; > /* Stall reason */ > __u8 stall_reason; > __u16 pad; > };
Kim, does this format indeed work for AMD IBS?