dw_pcie_host_init() calls .init before caching the offset. So inside .init we call dw_pcie_get_pcie_cap() to trigger caching. The helper will perform the DBI read (hardware is already enabled) and cache the result.
Signed-off-by: Hans Zhang <[email protected]> Reviewed-by: Sebastian Reichel <[email protected]> --- In pcie-dw-rockchip, the call chain is: static const struct dw_pcie_host_ops rockchip_pcie_host_ops = { .init = rockchip_pcie_host_init, }; rockchip_pcie_host_init() -> rockchip_pcie_enable_l0s() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 731d93663cca..be8b6187913d 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -369,7 +369,7 @@ static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) u32 cap, lnkcap; /* Enable L0S capability for all SoCs */ - cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + cap = dw_pcie_get_pcie_cap(pci); if (cap) { lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); lnkcap |= PCI_EXP_LNKCAP_ASPM_L0S; -- 2.34.1
