In host mode: tegra_pcie_dw_host_init() runs inside .start_link, which is called after dw_pcie_host_init() has cached the offset. However, the driver's own initialization already enables hardware, so calling dw_pcie_get_pcie_cap() is safe and will return the cached value.
In endpoint mode: pex_ep_event_pex_rst_deassert() runs after hardware is enabled (PERST# deassert). Because the core no longer caches automatically, we call dw_pcie_get_pcie_cap() here to cache the offset for subsequent accesses. The helper performs the DBI read only when hardware is ready. Thus, the private pcie_cap_base is always valid and can still be used for register accesses. Signed-off-by: Hans Zhang <[email protected]> --- In pcie-tegra194, dw_pcie_find_capability() appears in: static const struct dw_pcie_ops tegra_dw_pcie_ops = { .start_link = tegra_pcie_dw_start_link, }; tegra_pcie_dw_start_link() -> tegra_pcie_dw_host_init() -> dw_pcie_find_capability() tegra_pcie_dw_probe() case DW_PCIE_EP_TYPE: tegra_pcie_config_ep() -> pex_ep_event_pex_rst_deassert() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 795cef5a915d..bf482bc66a92 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -905,8 +905,7 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) pp->bridge->ops = &tegra_pci_ops; if (!pcie->pcie_cap_base) - pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, - PCI_CAP_ID_EXP); + pcie->pcie_cap_base = dw_pcie_get_pcie_cap(pci); val = dw_pcie_readl_dbi(pci, PCI_IO_BASE); val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); @@ -1889,8 +1888,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); } - pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, - PCI_CAP_ID_EXP); + pcie->pcie_cap_base = dw_pcie_get_pcie_cap(pci); /* Clear Slot Clock Configuration bit if SRNS configuration */ if (pcie->enable_srns) { -- 2.34.1
