On Mon, 2010-03-29 at 23:24 -0700, bruce_leon...@selinc.com wrote: > I'm tracking a problem that's leading me through DSI and DTLB miss > exceptions on an MPC8347 (e300c1 core), and I've come across an oddity > that I'm hoping someone can explain. > > When a DTLB Miss exception can't find a PTE for the virtual address being > written/read, it dummies up the SPRs for a DSI exception and then calls > directly into the DSI exception code. Just before the DTLB miss code > stores a value into DSISR it sets bit 2, which for a DSI exception is a > reserved bit and should be cleared. There's no comment on the code > (.../arch/powerpc/kernel/head_32.S line 619 of the 2.6.33-rc1 kernel). Can > anyone tell me why this bit is getting set?
You mean: 616 DataAddressInvalid: 617 mfspr r3,SPRN_SRR1 618 rlwinm r1,r3,9,6,6 /* Get load/store bit */ 619 addis r1,r1,0x2000 620 mtspr SPRN_DSISR,r1 Is it trying to set DSISR_ISSTORE? #define DSISR_ISSTORE 0x02000000 /* access was a store */ cheers
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