https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/196398
>From d7babc2fae6fcbd3d10d14071a5af6649e2c4f10 Mon Sep 17 00:00:00 2001 From: Petar Avramovic <[email protected]> Date: Thu, 7 May 2026 20:56:43 +0200 Subject: [PATCH] GlobalISel: Improve MMO extended LLT caclulation from size --- llvm/include/llvm/CodeGen/MachineFunction.h | 15 +++++++++------ .../CodeGen/AArch64/GlobalISel/legalize-and.mir | 4 ++-- .../AArch64/GlobalISel/legalize-load-store.mir | 4 ++-- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h index d620ae5137eba..5e34eab8c57e7 100644 --- a/llvm/include/llvm/CodeGen/MachineFunction.h +++ b/llvm/include/llvm/CodeGen/MachineFunction.h @@ -1158,12 +1158,15 @@ class LLVM_ABI MachineFunction { int64_t Offset, LLT Ty); MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO, int64_t Offset, LocationSize Size) { - return getMachineMemOperand( - MMO, Offset, - !Size.isPrecise() ? LLT() - : Size.isScalable() - ? LLT::scalable_vector(1, 8 * Size.getValue().getKnownMinValue()) - : LLT::scalar(8 * Size.getValue().getKnownMinValue())); + if (!Size.isPrecise()) + return getMachineMemOperand(MMO, Offset, LLT()); + + unsigned SizeInBits = 8 * Size.getValue().getKnownMinValue(); + LLT Ty = Size.isScalable() ? LLT::scalable_vector(1, SizeInBits) + : MMO->getType().isPointerOrPointerVector() + ? LLT::scalar(SizeInBits) + : MMO->getType().changeElementSize(SizeInBits); + return getMachineMemOperand(MMO, Offset, Ty); } MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO, int64_t Offset, uint64_t Size) { diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir index 252960568fe94..683e5523c9ad9 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir @@ -65,8 +65,8 @@ body: | ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[TRUNC]], [[C5]](i64) ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 2 ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C6]](i64) - ; CHECK-NEXT: G_STORE [[TRUNC]](i32), [[PTR_ADD3]](p0) :: (store (s16) into unknown-address + 8, align 8) - ; CHECK-NEXT: G_STORE [[LSHR]](i32), [[PTR_ADD4]](p0) :: (store (s8) into unknown-address + 10, align 2) + ; CHECK-NEXT: G_STORE [[TRUNC]](i32), [[PTR_ADD3]](p0) :: (store (i16) into unknown-address + 8, align 8) + ; CHECK-NEXT: G_STORE [[LSHR]](i32), [[PTR_ADD4]](p0) :: (store (i8) into unknown-address + 10, align 2) %ptr:_(p0) = COPY $x0 %a:_(i88) = G_LOAD %ptr(p0) :: (load (s88)) %b:_(i88) = G_LOAD %ptr(p0) :: (load (s88)) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir index ab4ecc5241a26..15c42aab0781b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir @@ -650,8 +650,8 @@ body: | ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[TRUNC]], [[C5]](i64) ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 2 ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD2]], [[C6]](i64) - ; CHECK-NEXT: G_STORE [[TRUNC]](i32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 8, align 8) - ; CHECK-NEXT: G_STORE [[LSHR]](i32), [[PTR_ADD3]](p0) :: (store (s8) into unknown-address + 10, align 2) + ; CHECK-NEXT: G_STORE [[TRUNC]](i32), [[PTR_ADD2]](p0) :: (store (i16) into unknown-address + 8, align 8) + ; CHECK-NEXT: G_STORE [[LSHR]](i32), [[PTR_ADD3]](p0) :: (store (i8) into unknown-address + 10, align 2) ; CHECK-NEXT: RET_ReallyLR %ptr:_(p0) = COPY $x0 %load:_(s88) = G_LOAD %ptr(p0) :: (load (s88)) _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
