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________________________________ From: Zafar Ali (zali) <[email protected]> Sent: Tuesday, July 21, 2026 11:38 PM To: Bonica, Ron <[email protected]>; lsr <[email protected]> Cc: Zafar Ali (zali) <[email protected]> Subject: Re: IS-IS Support for PCPPS Hi Ron What I highlighted is: how come someone who claims to have implemented this did not realize that the sleeping power is non-zero? [RB] Is this a technical question or an ad hominem attack? [RB] Recall that in many hardware architectures, sleeping power is zero. If I draw a dotted line, how does one ensure that the power-saving estimate for a given “power group” is accurate? [RB] Generally, hardware vendors publish this information. The questions Robert asked are valid and related. [RB] And answered in draft-many-teas-power-steering. What is the right data model? We need to ask the Green WG. [RB] The value of a data model is its descriptive efficiency. In this case, if a data model can describe any hardware architecture that you need to describe, it is good enough. [RB] Can you describe a hardware architecture that the data model cannot? If not, there is no valid criticism. Also, operators perform many capacity planning exercises to design the network. The operators need to consider what the implications are for shutting a “power group” What considerations must be in place before shutting down the "power groups"? Is this a good idea, or will it create more pain for network operations? [RB] In Section 3.3.4 of the draft, you will notice a power-sleep-capable bit. This bit is set only of the operator configures the interface to be power-sleep-capable. [RB] There are many reasons why an operator may determine that an interface is or is not power-save-capable. This is beyond the scope of this document. Thanks Regards … Zafar From: Bonica, Ron <[email protected]> Date: Monday, July 20, 2026 at 3:55 AM To: lsr <[email protected]>; Zafar Ali (zali) <[email protected]> Subject: IS-IS Support for PCPPS Zafar, If I understood your comment during the IETF 126 session correctly, you said that the Power Group model may not support some existing hardware architectures. Can you describe such an architecture? Ron
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